changeset fb13c36c3951 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fb13c36c3951
description:
X86: Read the LDT/GDT at CPL0 when executing an iret.
During iret access LDT/GDT at CPL0 rather than after transition to user
mode
(if I'm reading the Intel IA-64 architecture spec correctly, the
contents of
the descriptor table are read before the CPL is updated).
diffstat:
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
| 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diffs (29 lines):
diff -r 68f37178b408 -r fb13c36c3951
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Mon Feb 07 12:42:23 2011 -0600
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Mon Feb 07 15:05:28 2011 -0800
@@ -102,10 +102,10 @@
andi t6, t2, 0xF8, dataSize=8
andi t0, t2, 0x4, flags=(EZF,), dataSize=2
br label("globalCSDescriptor"), flags=(CEZF,)
- ld t8, tsl, [1, t0, t6], dataSize=8
+ ld t8, tsl, [1, t0, t6], dataSize=8, atCPL0=True
br label("processCSDescriptor")
globalCSDescriptor:
- ld t8, tsg, [1, t0, t6], dataSize=8
+ ld t8, tsg, [1, t0, t6], dataSize=8, atCPL0=True
processCSDescriptor:
chks t2, t6, dataSize=8
@@ -159,10 +159,10 @@
andi t7, t9, 0xF8, dataSize=8
andi t0, t9, 0x4, flags=(EZF,), dataSize=2
br label("globalSSDescriptor"), flags=(CEZF,)
- ld t7, tsl, [1, t0, t7], dataSize=8
+ ld t7, tsl, [1, t0, t7], dataSize=8, atCPL0=True
br label("processSSDescriptor")
globalSSDescriptor:
- ld t7, tsg, [1, t0, t7], dataSize=8
+ ld t7, tsg, [1, t0, t7], dataSize=8, atCPL0=True
processSSDescriptor:
chks t9, t7, dataSize=8
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
