changeset e00ef55a2c49 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e00ef55a2c49
description:
X86: Obey the wp bit of CR0.
If cr0.wp ("write protect" bit) is clear then do not generate page
faults when
writing to write-protected pages in kernel mode.
diffstat:
src/arch/x86/tlb.cc | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diffs (22 lines):
diff -r 6220632e8636 -r e00ef55a2c49 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Mon Feb 07 15:16:27 2011 -0800
+++ b/src/arch/x86/tlb.cc Mon Feb 07 15:18:52 2011 -0800
@@ -634,14 +634,15 @@
// Do paging protection checks.
bool inUser = (m5Reg.cpl == 3 &&
!(flags & (CPL0FlagBit << FlagShift)));
- if ((inUser && !entry->user) ||
- (mode == Write && !entry->writable)) {
+ CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
+ bool badWrite = (!entry->writable && (inUser || cr0.wp));
+ if ((inUser && !entry->user) || (mode == Write && badWrite)) {
// The page must have been present to get into the TLB in
// the first place. We'll assume the reserved bits are
// fine even though we're not checking them.
return new PageFault(vaddr, true, mode, inUser, false);
}
- if (storeCheck && !entry->writable) {
+ if (storeCheck && badWrite) {
// This would fault if this were a write, so return a page
// fault that reflects that happening.
return new PageFault(vaddr, true, Write, inUser, false);
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