changeset 32758425de8c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=32758425de8c
description:
SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side
walk occurs.
This change fixes an issue where a DTLB fault occurs and redirects
fetch to
handle the fault and the ITLB requires a walk which delays translation.
In this
case the status of the cpu isn't updated appropriately, and an
additional
instruction fetch occurs. Eventually this hits an assert as multiple
instruction
fetches are occuring in the system and when the second one returns the
processor is in the wrong state.
Some asserts below are removed because it was always true (typo) and
the state
after the initiateAcc() the processor could be in any valid state when a
d-side fault occurs.
diffstat:
src/cpu/simple/timing.cc | 12 ++++++------
src/cpu/simple/timing.hh | 5 ++++-
2 files changed, 10 insertions(+), 7 deletions(-)
diffs (44 lines):
diff -r 1daf51f62013 -r 32758425de8c src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Fri Feb 11 18:29:35 2011 -0600
+++ b/src/cpu/simple/timing.cc Fri Feb 11 18:29:35 2011 -0600
@@ -752,6 +752,7 @@
} else {
delete req;
// fetch fault: advance directly to next instruction (fault handler)
+ _status = Running;
advanceInst(fault);
}
@@ -805,12 +806,11 @@
if (curStaticInst && curStaticInst->isMemRef()) {
// load or store: just send to dcache
Fault fault = curStaticInst->initiateAcc(this, traceData);
- if (_status != Running) {
- // instruction will complete in dcache response callback
- assert(_status == DcacheWaitResponse ||
- _status == DcacheRetry || DTBWaitResponse);
- assert(fault == NoFault);
- } else {
+
+ // If we're not running now the instruction will complete in a dcache
+ // response callback or the instruction faulted and has started an
+ // ifetch
+ if (_status == Running) {
if (fault != NoFault && traceData) {
// If there was a fault, we shouldn't trace this instruction.
delete traceData;
diff -r 1daf51f62013 -r 32758425de8c src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh Fri Feb 11 18:29:35 2011 -0600
+++ b/src/cpu/simple/timing.hh Fri Feb 11 18:29:35 2011 -0600
@@ -109,7 +109,10 @@
void
markDelayed()
- {}
+ {
+ assert(cpu->_status == Running);
+ cpu->_status = ITBWaitResponse;
+ }
void
finish(Fault fault, RequestPtr req, ThreadContext *tc,
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