changeset 6d07db809a81 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6d07db809a81
description:
O3: Fix pipeline restart when a table walk completes in the fetch stage.
When a table walk is initiated by the fetch stage, the CPU can
potentially move to the idle state and never wake up.
The fetch stage must call cpu->wakeCPU() when a translation completes
(in finishTranslation()).
diffstat:
src/cpu/o3/fetch_impl.hh | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diffs (23 lines):
diff -r 7c58c106d28d -r 6d07db809a81 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Fri Feb 11 18:29:35 2011 -0600
+++ b/src/cpu/o3/fetch_impl.hh Fri Feb 11 18:29:35 2011 -0600
@@ -604,6 +604,9 @@
ThreadID tid = mem_req->threadId();
Addr block_PC = mem_req->getVaddr();
+ // Wake up CPU if it was idle
+ cpu->wakeCPU();
+
// If translation was successful, attempt to read the icache block.
if (fault == NoFault) {
// Build packet here.
@@ -654,6 +657,9 @@
instruction->fault = fault;
wroteToTimeBuffer = true;
+ DPRINTF(Activity, "Activity this cycle.\n");
+ cpu->activityThisCycle();
+
fetchStatus[tid] = TrapPending;
DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
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