changeset 896a68fc68dc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=896a68fc68dc
description:
inorder: remove unused isa ops
pass/fail ops were used for testing but arent part of isa
diffstat:
src/arch/mips/isa/decoder.isa | 16 +---------------
1 files changed, 1 insertions(+), 15 deletions(-)
diffs (26 lines):
diff -r 6548721032fa -r 896a68fc68dc src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Fri Feb 11 18:29:36 2011 -0600
+++ b/src/arch/mips/isa/decoder.isa Sat Feb 12 10:14:26 2011 -0500
@@ -367,21 +367,7 @@
}});
0x1: addiu({{ Rt.sw = Rs.sw + imm; }});
0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }});
-
- //Edited to include MIPS AVP Pass/Fail instructions and
- //default to the sltiu instruction
- 0x3: decode RS_RT_INTIMM {
- 0xabc1: BasicOp::fail({{
- exitSimLoop("AVP/SRVP Test Failed");
- }});
- 0xabc2: BasicOp::pass({{
- exitSimLoop("AVP/SRVP Test Passed");
- }});
- default: sltiu({{
- Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0;
- }});
- }
-
+ 0x3: sltiu({{ Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0;}});
0x4: andi({{ Rt.sw = Rs.sw & zextImm; }});
0x5: ori({{ Rt.sw = Rs.sw | zextImm; }});
0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }});
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