changeset 682275767ec3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=682275767ec3
description:
inorder: cache instruction schedules
first step in a optimization to not dynamically allocate an instruction
schedule
for every instruction but rather used cached schedules
diffstat:
src/cpu/inorder/cpu.cc | 6 +++-
src/cpu/inorder/cpu.hh | 56 ++++++++++++++++++++++++++++++++++++++
src/cpu/inorder/pipeline_traits.hh | 1 +
3 files changed, 62 insertions(+), 1 deletions(-)
diffs (110 lines):
diff -r 1da241308c1b -r 682275767ec3 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sat Feb 12 10:14:34 2011 -0500
+++ b/src/cpu/inorder/cpu.cc Sat Feb 12 10:14:36 2011 -0500
@@ -334,9 +334,13 @@
dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyReqInst->setSquashed();
+ dummyReqInst->resetInstCount();
dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyBufferInst->setSquashed();
+ dummyBufferInst->resetInstCount();
+
+ endOfSkedIt = skedCache.end();
lastRunningCycle = curTick();
@@ -348,7 +352,6 @@
reset();
#endif
- dummyBufferInst->resetInstCount();
// Schedule First Tick Event, CPU will reschedule itself from here on out.
scheduleTickEvent(0);
@@ -359,6 +362,7 @@
delete resPool;
}
+std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
void
InOrderCPU::regStats()
diff -r 1da241308c1b -r 682275767ec3 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sat Feb 12 10:14:34 2011 -0500
+++ b/src/cpu/inorder/cpu.hh Sat Feb 12 10:14:36 2011 -0500
@@ -296,6 +296,62 @@
TheISA::TLB *getITBPtr();
TheISA::TLB *getDTBPtr();
+ /** Accessor Type for the SkedCache */
+ typedef uint32_t SkedID;
+
+ /** Cache of Instruction Schedule using the instruction's name as a key */
+ static std::map<SkedID, ThePipeline::RSkedPtr> skedCache;
+
+ typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
+
+ /** Initialized to last iterator in map, signifying a invalid entry
+ on map searches
+ */
+ SkedCacheIt endOfSkedIt;
+
+ /** Add a new instruction schedule to the schedule cache */
+ void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
+ {
+ SkedID sked_id = genSkedID(inst);
+ skedCache[sked_id] = inst_sked;
+ }
+
+
+ /** Find a instruction schedule */
+ ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
+ {
+ SkedID sked_id = genSkedID(inst);
+ SkedCacheIt lookup_it = skedCache.find(sked_id);
+
+ if (lookup_it != endOfSkedIt) {
+ return (*lookup_it).second;
+ } else {
+ return NULL;
+ }
+ }
+
+ static const uint8_t INST_OPCLASS = 26;
+ static const uint8_t INST_LOAD = 25;
+ static const uint8_t INST_STORE = 24;
+ static const uint8_t INST_CONTROL = 23;
+ static const uint8_t INST_NONSPEC = 22;
+ static const uint8_t INST_DEST_REGS = 18;
+ static const uint8_t INST_SRC_REGS = 14;
+
+ inline SkedID genSkedID(DynInstPtr inst)
+ {
+ SkedID id = 0;
+ id = (inst->opClass() << INST_OPCLASS) |
+ (inst->isLoad() << INST_LOAD) |
+ (inst->isStore() << INST_STORE) |
+ (inst->isControl() << INST_CONTROL) |
+ (inst->isNonSpeculative() << INST_NONSPEC) |
+ (inst->numDestRegs() << INST_DEST_REGS) |
+ (inst->numSrcRegs() << INST_SRC_REGS);
+ return id;
+ }
+
+
public:
/** Registers statistics. */
diff -r 1da241308c1b -r 682275767ec3 src/cpu/inorder/pipeline_traits.hh
--- a/src/cpu/inorder/pipeline_traits.hh Sat Feb 12 10:14:34 2011 -0500
+++ b/src/cpu/inorder/pipeline_traits.hh Sat Feb 12 10:14:36 2011 -0500
@@ -77,6 +77,7 @@
// RESOURCE SCHEDULING
//////////////////////////
typedef ResourceSked ResSchedule;
+ typedef ResourceSked* RSkedPtr;
void createFrontEndSchedule(DynInstPtr &inst);
bool createBackEndSchedule(DynInstPtr &inst);
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