changeset be8762db2561 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=be8762db2561 description: X86: Only reset npc to reflect instruction length once.
When redirecting fetch to handle branches, the npc of the current pc state needs to be left alone. This change makes the pc state record whether or not the npc already reflects a real value by making it keep track of the current instruction size, or if no size has been set. diffstat: src/arch/x86/predecoder.hh | 6 ++++- src/arch/x86/types.hh | 50 +++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 2 deletions(-) diffs (76 lines): diff -r 6d955240bb62 -r be8762db2561 src/arch/x86/predecoder.hh --- a/src/arch/x86/predecoder.hh Sun Feb 13 17:40:07 2011 -0800 +++ b/src/arch/x86/predecoder.hh Sun Feb 13 17:41:10 2011 -0800 @@ -225,7 +225,11 @@ { assert(emiIsReady); emiIsReady = false; - nextPC.npc(nextPC.pc() + getInstSize()); + if (!nextPC.size()) { + Addr size = getInstSize(); + nextPC.size(size); + nextPC.npc(nextPC.pc() + size); + } return emi; } }; diff -r 6d955240bb62 -r be8762db2561 src/arch/x86/types.hh --- a/src/arch/x86/types.hh Sun Feb 13 17:40:07 2011 -0800 +++ b/src/arch/x86/types.hh Sun Feb 13 17:41:10 2011 -0800 @@ -222,7 +222,55 @@ return true; } - typedef GenericISA::UPCState<MachInst> PCState; + class PCState : public GenericISA::UPCState<MachInst> + { + protected: + typedef GenericISA::UPCState<MachInst> Base; + + uint8_t _size; + + public: + void + set(Addr val) + { + Base::set(val); + _size = 0; + } + + PCState() {} + PCState(Addr val) { set(val); } + + uint8_t size() const { return _size; } + void size(uint8_t newSize) { _size = newSize; } + + void + advance() + { + Base::advance(); + _size = 0; + } + + void + uEnd() + { + Base::uEnd(); + _size = 0; + } + + void + serialize(std::ostream &os) + { + Base::serialize(os); + SERIALIZE_SCALAR(_size); + } + + void + unserialize(Checkpoint *cp, const std::string §ion) + { + Base::unserialize(cp, section); + UNSERIALIZE_SCALAR(_size); + } + }; struct CoreSpecific { int core_type; _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev