changeset 068f061e57a8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=068f061e57a8
description:
X86: Put the result used for flags in an intermediate variable.
Using the destination register directly causes the ISA parser to treat
it as a
source even if none of the original bits are used.
diffstat:
src/arch/x86/insts/microregop.cc | 3 --
src/arch/x86/isa/includes.isa | 1 +
src/arch/x86/isa/microops/regop.isa | 38 ++++++++++++++++++++----------------
3 files changed, 22 insertions(+), 20 deletions(-)
diffs (128 lines):
diff -r e64e90b862a7 -r 068f061e57a8 src/arch/x86/insts/microregop.cc
--- a/src/arch/x86/insts/microregop.cc Sun Feb 13 17:44:32 2011 -0800
+++ b/src/arch/x86/insts/microregop.cc Sun Feb 13 17:45:12 2011 -0800
@@ -50,9 +50,6 @@
bool subtract) const
{
DPRINTF(X86, "flagMask = %#x\n", flagMask);
- if (_destRegIdx[0] & IntFoldBit) {
- _dest >>= 8;
- }
uint64_t flags = oldFlags & ~flagMask;
if(flagMask & (ECFBit | CFBit))
{
diff -r e64e90b862a7 -r 068f061e57a8 src/arch/x86/isa/includes.isa
--- a/src/arch/x86/isa/includes.isa Sun Feb 13 17:44:32 2011 -0800
+++ b/src/arch/x86/isa/includes.isa Sun Feb 13 17:45:12 2011 -0800
@@ -114,6 +114,7 @@
#include "arch/x86/regs/misc.hh"
#include "arch/x86/tlb.hh"
#include "base/bigint.hh"
+#include "base/compiler.hh"
#include "base/condcodes.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
diff -r e64e90b862a7 -r 068f061e57a8 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Sun Feb 13 17:44:32 2011 -0800
+++ b/src/arch/x86/isa/microops/regop.isa Sun Feb 13 17:45:12 2011 -0800
@@ -51,6 +51,8 @@
%(op_decl)s;
%(op_rd)s;
+ IntReg result M5_VAR_USED;
+
if(%(cond_check)s)
{
%(code)s;
@@ -79,6 +81,8 @@
%(op_decl)s;
%(op_rd)s;
+ IntReg result M5_VAR_USED;
+
if(%(cond_check)s)
{
%(code)s;
@@ -434,7 +438,7 @@
flag_code = '''
//Don't have genFlags handle the OF or CF bits
uint64_t mask = CFBit | ECFBit | OFBit;
- ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1,
op2);
+ ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2);
//If a logic microop wants to set these, it wants to set them to 0.
ccFlagBits &= ~(CFBit & ext);
ccFlagBits &= ~(ECFBit & ext);
@@ -444,12 +448,12 @@
class FlagRegOp(RegOp):
abstract = True
flag_code = \
- "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
+ "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
class SubRegOp(RegOp):
abstract = True
flag_code = \
- "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2,
true);"
+ "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2,
true);"
class CondRegOp(RegOp):
abstract = True
@@ -471,44 +475,44 @@
src1, src2, flags, dataSize)
class Add(FlagRegOp):
- code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
- big_code = 'DestReg = (psrc1 + op2) & mask(dataSize * 8);'
+ code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
+ big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
class Or(LogicRegOp):
- code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
- big_code = 'DestReg = (psrc1 | op2) & mask(dataSize * 8);'
+ code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);'
+ big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
class Adc(FlagRegOp):
code = '''
CCFlagBits flags = ccFlagBits;
- DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
+ DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf),
dataSize);
'''
big_code = '''
CCFlagBits flags = ccFlagBits;
- DestReg = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
+ DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
'''
class Sbb(SubRegOp):
code = '''
CCFlagBits flags = ccFlagBits;
- DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
+ DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf),
dataSize);
'''
big_code = '''
CCFlagBits flags = ccFlagBits;
- DestReg = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
+ DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
'''
class And(LogicRegOp):
- code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
- big_code = 'DestReg = (psrc1 & op2) & mask(dataSize * 8)'
+ code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)'
+ big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
class Sub(SubRegOp):
- code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
- big_code = 'DestReg = (psrc1 - op2) & mask(dataSize * 8)'
+ code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
+ big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
class Xor(LogicRegOp):
- code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
- big_code = 'DestReg = (psrc1 ^ op2) & mask(dataSize * 8)'
+ code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)'
+ big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
class Mul1s(WrRegOp):
code = '''
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