changeset 2e7177da9ea5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2e7177da9ea5
description:
update platform code to use PALTemp Whami register to get cpu id
instead of reading register from tsunami chipset, saving an uncached
read
diffstat:
system/alpha/palcode/platform_m5.s | 33 +-
system/alpha/palcode/platform_srcmax.s | 1894 --------------------------------
2 files changed, 17 insertions(+), 1910 deletions(-)
diffs (truncated from 1976 to 300 lines):
diff -r fa59ff6f1526 -r 2e7177da9ea5 system/alpha/palcode/platform_m5.s
--- a/system/alpha/palcode/platform_m5.s Wed Oct 06 11:27:46 2004 -0400
+++ b/system/alpha/palcode/platform_m5.s Tue Nov 23 02:01:30 2004 -0500
@@ -743,19 +743,19 @@
//-
ALIGN_BRANCH
sys_int_23:
- or r31,0,r16 // IPI interrupt A0 = 0
+ or r31,0,r16 // IPI interrupt A0 = 0
lda r12,0xf01(r31) // build up an address for
the MISC register
sll r12,16,r12
lda r12,0xa000(r12)
sll r12,16,r12
lda r12,0x080(r12)
- ldq_p r10,0(r12) // read misc register
- and r10,0x3,r10 // isolate CPUID
+ mfpr r10, pt_whami // get CPU ID
+ extbl r10, 1, r10 // Isolate just whami bits
or r31,0x1,r14 // load r14 with bit to clear
- sll r14,r10,r14 // left shift by CPU ID
+ sll r14,r10,r14 // left shift by CPU ID
sll r14,8,r14
- stq_p r14, 0(r12) // clear the rtc interrupt
+ stq_p r14, 0(r12) // clear the rtc interrupt
br r31, pal_post_interrupt // Notify the OS
@@ -763,17 +763,17 @@
ALIGN_BRANCH
sys_int_22:
or r31,1,r16 // a0 means it is a clock
interrupt
- lda r12,0xf01(r31) // build up an address for
the MISC register
+ lda r12,0xf01(r31) // build up an address for the
MISC register
sll r12,16,r12
lda r12,0xa000(r12)
sll r12,16,r12
lda r12,0x080(r12)
- ldq_p r10,0(r12) // read misc register
- and r10,0x3,r10 // isolate CPUID
- or r31,0x10,r14 // load r14 with bit to clear
- sll r14,r10,r14 // left shift by CPU ID
- stq_p r14, 0(r12) // clear the rtc interrupt
+ mfpr r10, pt_whami // get CPU ID
+ extbl r10, 1, r10 // Isolate just whami bits
+ or r31,0x10,r14 // load r14 with bit to clear
+ sll r14,r10,r14 // left shift by CPU ID
+ stq_p r14, 0(r12) // clear the rtc interrupt
br r31, pal_post_interrupt // Tell the OS
@@ -816,19 +816,20 @@
sll r13,8,r13
bis r12,r13,r12
lda r12,0x0080(r12)
- ldqp r13, 0(r12) // read the MISC register for
CPUID
+ mfpr r13, pt_whami // get CPU ID
+ extbl r13, 1, r10 // Isolate just whami bits
- and r13,0x1,r14 // grab LSB and shift left 6
+ and r13,0x1,r14 // grab LSB and shift left 6
sll r14,6,r14
- and r13,0x2,r10 // grabl LSB+1 and shift left 9
+ and r13,0x2,r10 // grabl LSB+1 and shift left 9
sll r10,9,r10
- mskbl r12,0,r12 // calculate DIRn address
+ mskbl r12,0,r12 // calculate DIRn address
lda r13,0x280(r31)
bis r12,r13,r12
or r12,r14,r12
or r12,r10,r12
- ldqp r13, 0(r12) // read DIRn
+ ldqp r13, 0(r12) // read DIRn
or r31,1,r14 // set bit 55 (ISA Interrupt)
sll r14,55,r14
diff -r fa59ff6f1526 -r 2e7177da9ea5 system/alpha/palcode/platform_srcmax.s
--- a/system/alpha/palcode/platform_srcmax.s Wed Oct 06 11:27:46 2004 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1894 +0,0 @@
-// build_fixed_image: not sure what means
-// real_mm to be replaced during rewrite
-// remove_save_state remove_restore_state can be remooved to save space ??
-#define egore 0
-#define acore 0
-#define beh_model 0
-#define ev5_p2 1
-#define ev5_p1 0
-#define ldvpte_bug_fix 1
-#define spe_fix 0
-#define osf_chm_fix 0
-#define build_fixed_image 0
-#define enable_p4_fixups 0
-#define osf_svmin 1
-#define enable_physical_console 0
-#define fill_err_hack 0
-#define icflush_on_tbix 0
-#define max_cpuid 1
-#define perfmon_debug 0
-#define rax_mode 0
-
-#define hw_rei_spe hw_rei
-
-#include "ev5_defs.h"
-#include "ev5_impure.h"
-#include "ev5_alpha_defs.h"
-#include "ev5_paldef.h"
-#include "ev5_osfalpha_defs.h"
-#include "fromHudsonMacros.h"
-#include "fromHudsonOsf.h"
-#include "dc21164FromGasSources.h"
-#include "cserve.h"
-
-#define ldlp ldl_p
-#define ldqp ldq_p
-#define stqp stq_p
-#define stqpc stqp
-
-#define pt_entInt pt_entint
-#define pt_entArith pt_entarith
-#define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8)
-#define mchk_flag CNS_Q_FLAG
-#define mchk_sys_base 56
-#define mchk_cpu_base (CNS_Q_LD_LOCK + 8)
-#define mchk_offsets CNS_Q_EXC_ADDR
-#define mchk_mchk_code 8
-#define mchk_ic_perr_stat CNS_Q_ICPERR_STAT
-#define mchk_dc_perr_stat CNS_Q_DCPERR_STAT
-#define mchk_sc_addr CNS_Q_SC_ADDR
-#define mchk_sc_stat CNS_Q_SC_STAT
-#define mchk_ei_addr CNS_Q_EI_ADDR
-#define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR
-#define mchk_fill_syn CNS_Q_FILL_SYN
-#define mchk_ei_stat CNS_Q_EI_STAT
-#define mchk_exc_addr CNS_Q_EXC_ADDR
-#define mchk_ld_lock CNS_Q_LD_LOCK
-#define osfpcb_q_Ksp pcb_q_ksp
-#define pal_impure_common_size ((0x200 + 7) & 0xfff8)
-
-#define RTCADD 0x160000
-#define RTCDAT 0x170000
-
-/* Serial Port (COM) Definitions: */
-#define DLA_K_BRG 12 /* Baud Rate Divisor = 9600 */
-
-#define LSR_V_THRE 5 /* Xmit Holding Register Empty Bit */
-
-#define LCR_M_WLS 3 /* Word Length Select Mask */
-#define LCR_M_STB 4 /* Number Of Stop Bits Mask */
-#define LCR_M_PEN 8 /* Parity Enable Mask */
-#define LCR_M_DLAB 128 /* Divisor Latch Access Bit Mask */
-
-#define LCR_K_INIT (LCR_M_WLS | LCR_M_STB)
-
-#define MCR_M_DTR 1 /* Data Terminal Ready Mask */
-#define MCR_M_RTS 2 /* Request To Send Mask */
-#define MCR_M_OUT1 4 /* Output 1 Control Mask */
-#define MCR_M_OUT2 8 /* UART Interrupt Mask Enable */
-
-#define MCR_K_INIT (MCR_M_DTR | \
- MCR_M_RTS | \
- MCR_M_OUT1 | \
- MCR_M_OUT2)
-#define SLOT_D_COM1 (0x140000)
-#define COM1_RBR (SLOT_D_COM1 | (0x0 << 1)) /* Receive Buffer Register Offset
*/
-#define COM1_THR (SLOT_D_COM1 | (0x0 << 1)) /* Xmit Holding Register Offset */
-#define COM1_IER (SLOT_D_COM1 | (0x1 << 1)) /* Interrupt Enable Register Offset
-*/
-#define COM1_IIR (SLOT_D_COM1 | (0x2 << 1)) /* Interrupt ID Register Offset */
-#define COM1_LCR (SLOT_D_COM1 | (0x3 << 1)) /* Line Control Register Offset */
-#define COM1_MCR (SLOT_D_COM1 | (0x4 << 1)) /* Modem Control Register Offset */
-#define COM1_LSR (SLOT_D_COM1 | (0x5 << 1)) /* Line Status Register Offset */
-#define COM1_MSR (SLOT_D_COM1 | (0x6 << 1)) /* Modem Status Register Offset */
-#define COM1_SCR (SLOT_D_COM1 | (0x7 << 1)) /* Scratch Register Offset */
-#define COM1_DLL (SLOT_D_COM1 | (0x8 << 1)) /* Divisor Latch (LS) Offset */
-#define COM1_DLH (SLOT_D_COM1 | (0x9 << 1)) /* Divisor Latch (MS) Offset */
-
-
-#define BYTE_ENABLE_SHIFT 5
-#define PCI_MEM 0x400
-
-#ifdef SIMOS
-#define OutPortByte(port,val,a,b)
-#define InPortByte(port,val,a)
-#else
-
-#define OutPortByte(port,val,tmp0,tmp1) \
- LDLI (tmp0, port); \
- sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
- lda tmp1, PCI_MEM(zero); \
- sll tmp1, 29, tmp1; \
- bis tmp0, tmp1, tmp0; \
- lda tmp1, (val)(zero); \
- sll tmp1, 8*(port & 3), tmp1; \
- stl_p tmp1, 0x00(tmp0); \
- mb
-
-#define InPortByte(port,tmp0,tmp1) \
- LDLI (tmp0, port); \
- sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
- lda tmp1, PCI_MEM(zero); \
- sll tmp1, 29, tmp1; \
- bis tmp0, tmp1, tmp0; \
- ldl_p tmp0, 0x00(tmp0); \
- srl tmp0, (8 * (port & 3)), tmp0; \
- zap tmp0, 0xfe, tmp0
-#endif
-
-#define r0 $0
-#define r1 $1
-#define r2 $2
-#define r3 $3
-#define r4 $4
-#define r5 $5
-#define r6 $6
-#define r7 $7
-#define r8 $8
-#define r9 $9
-#define r10 $10
-#define r11 $11
-#define r12 $12
-#define r13 $13
-#define r14 $14
-#define r15 $15
-#define r16 $16
-#define r17 $17
-#define r18 $18
-#define r19 $19
-#define r20 $20
-#define r21 $21
-#define r22 $22
-#define r23 $23
-#define r24 $24
-#define r25 $25
-#define r26 $26
-#define r27 $27
-#define r28 $28
-#define r29 $29
-#define r30 $30
-#define r31 $31
-
-#ifdef SIMOS
-#define DEBUGSTORE(c)
-#define DEBUG_EXC_ADDR()
-#else
-#define DEBUGSTORE(c) \
- lda r13, c(zero) ; \
- bsr r25, debugstore
-
-#define DEBUG_EXC_ADDR() \
- bsr r25, put_exc_addr; \
- DEBUGSTORE(13) ; \
- DEBUGSTORE(10)
-
-#endif /* SIMOS */
-
-#define ALIGN_BLOCK \
- .align 5
-
-#define ALIGN_BRANCH \
- .align 3
-
-// This module is for all the OSF system specific code.
-// This version is for the EV5 behavioral model.
-// .sbttl "Edit History"
-//+
-// Who Rev When What
-// ------------ --- ----------- --------------------------------
-//
-// [ deleted several pages of checking comments to make the file smaller -
lance ]
-//
-// PALcode merge done here .... JRH ....8/30/94
-// JM 1.00 1-aug-1994 Add support for pass2 to sys_perfmon
code
-// JM 1.01 2-aug-1994 Initialize cns_bc_config in reset
-// JM 1.02 5-aug-1994 Add ARITH_AND_MCHK routine.
-// Fix typo in bc_config init in rax
reset flow.
-// JM 1.03 19-aug-1994 BUG: sys_perfmon not generating mux
control mask properly, overwriting counters 0 & 1;
-// mode select masks
messed up too.
-//
-// JH 1.03A 26-Oct-1994 Log PCI error2 register ...needed for
CIA Pass 2 support
-//
-// JM 1.04 16-sep-1994 Moved perfmon code to ev5_osf_pal.m64
-// JM 1.05 9-jan-1995 Fix to EI_STAT entry in MCHK logout
frame -- OR in lower 28 bits (previously wiped out)
-// JM 1.06 2-feb-1995 Change "HW_REI" to "HW_REI_SPE"
everywhere that we may be changing to kernel mode from user
-// (part of super-page bug fix).
-// Initialize DC_TEST_CTL in reset flow.
-//
-// PALcode merge done here .... TLC ....02/06/95
-//
-// JM 1.07 3-mar-1995 Add init of dc_test_ctl; fix pvc_jsr
statement in ret from set_sc_bc_ctl
-// ES 1.08 17-mar-1995 Add osf_chm_fix to disable dcache in
reset
-//
-// PALcode merge done here .... TLC ....03/21/95
-//
-//
-// Entry points
-// SYS_CFLUSH - Cache flush
-// SYS_CSERVE - Console service
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