changeset d536bebb511d in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d536bebb511d description: inorder: initialize res. req. vectors based on resource bandwidth first change in an optimization that will stop InOrder from allocating new memory for every instruction's request to a resource. This gets expensive since every instruction needs to access ~10 requests before graduation. Instead, the plan is to allocate just enough resource request objects to satisfy each resource's bandwidth (e.g. the execution unit would need to allocate 3 resource request objects for a 1-issue pipeline since on any given cycle it could have 2 read requests and 1 write request) and then let the instructions contend and reuse those allocated requests. The end result is a smaller memory footprint for the InOrder model and increased simulation performance
diffstat: src/cpu/inorder/resource.cc | 6 ++++++ src/cpu/inorder/resource.hh | 2 ++ src/cpu/inorder/resources/cache_unit.cc | 5 +++++ src/cpu/inorder/resources/use_def.cc | 13 +++++++++++++ src/cpu/inorder/resources/use_def.hh | 2 ++ 5 files changed, 28 insertions(+), 0 deletions(-) diffs (85 lines): diff -r 68a5b8bba293 -r d536bebb511d src/cpu/inorder/resource.cc --- a/src/cpu/inorder/resource.cc Sat Feb 12 10:14:52 2011 -0500 +++ b/src/cpu/inorder/resource.cc Fri Feb 18 14:27:52 2011 -0500 @@ -40,6 +40,8 @@ : resName(res_name), id(res_id), width(res_width), latency(res_latency), cpu(_cpu) { + reqs.resize(width); + // Use to deny a instruction a resource. deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0); } @@ -57,6 +59,10 @@ // Set Up Resource Events to Appropriate Resource BandWidth resourceEvent = new ResourceEvent[width]; + for (int i = 0; i < width; i++) { + reqs[i] = new ResourceRequest(this, NULL, 0, 0, 0, 0); + } + initSlots(); } diff -r 68a5b8bba293 -r d536bebb511d src/cpu/inorder/resource.hh --- a/src/cpu/inorder/resource.hh Sat Feb 12 10:14:52 2011 -0500 +++ b/src/cpu/inorder/resource.hh Fri Feb 18 14:27:52 2011 -0500 @@ -224,6 +224,8 @@ /** Mapping of slot-numbers to the resource-request pointers */ std::map<int, ResReqPtr> reqMap; + std::vector<ResReqPtr> reqs; + /** A list of all the available execution slots for this resource. * This correlates with the actual resource event idx. */ diff -r 68a5b8bba293 -r d536bebb511d src/cpu/inorder/resources/cache_unit.cc --- a/src/cpu/inorder/resources/cache_unit.cc Sat Feb 12 10:14:52 2011 -0500 +++ b/src/cpu/inorder/resources/cache_unit.cc Fri Feb 18 14:27:52 2011 -0500 @@ -133,6 +133,11 @@ void CacheUnit::init() { + for (int i = 0; i < width; i++) { + reqs[i] = new CacheRequest(this, NULL, 0, 0, 0, 0, 0, + MemCmd::Command(0), 0, 0, 0); + } + // Currently Used to Model TLB Latency. Eventually // Switch to Timing TLB translations. resourceEvent = new CacheUnitEvent[width]; diff -r 68a5b8bba293 -r d536bebb511d src/cpu/inorder/resources/use_def.cc --- a/src/cpu/inorder/resources/use_def.cc Sat Feb 12 10:14:52 2011 -0500 +++ b/src/cpu/inorder/resources/use_def.cc Fri Feb 18 14:27:52 2011 -0500 @@ -88,6 +88,19 @@ Resource::regStats(); } +void +UseDefUnit::init() +{ + // Set Up Resource Events to Appropriate Resource BandWidth + resourceEvent = new ResourceEvent[width]; + + for (int i = 0; i < width; i++) { + reqs[i] = new UseDefRequest(this, NULL, 0, 0, 0, 0, 0); + } + + initSlots(); +} + ResReqPtr UseDefUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, int slot_num, unsigned cmd) diff -r 68a5b8bba293 -r d536bebb511d src/cpu/inorder/resources/use_def.hh --- a/src/cpu/inorder/resources/use_def.hh Sat Feb 12 10:14:52 2011 -0500 +++ b/src/cpu/inorder/resources/use_def.hh Fri Feb 18 14:27:52 2011 -0500 @@ -56,6 +56,8 @@ UseDefUnit(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); + void init(); + ResourceRequest* getRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num, unsigned cmd); _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev