changeset de6e9c30ad87 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=de6e9c30ad87
description:
inorder: remove request map, use request vector
take away all instances of reqMap in the code and make all references
use the built-in
request vectors inside of each resource. The request map was
dynamically allocating
a request per instruction. The request vector just allocates N number
of requests
during instantiation and then the surrounding code is fixed up to reuse
those N requests
***
setRequest() and clearRequest() are the new accessors needed to define
a new
request in a resource
diffstat:
src/cpu/inorder/cpu.cc | 7 +-
src/cpu/inorder/pipeline_stage.cc | 1 +
src/cpu/inorder/resource.cc | 153 ++++++++-----------------
src/cpu/inorder/resource.hh | 21 ++-
src/cpu/inorder/resources/agen_unit.cc | 4 +-
src/cpu/inorder/resources/branch_predictor.cc | 2 +-
src/cpu/inorder/resources/cache_unit.cc | 69 ++++-------
src/cpu/inorder/resources/cache_unit.hh | 43 +++++-
src/cpu/inorder/resources/decode_unit.cc | 4 +-
src/cpu/inorder/resources/execution_unit.cc | 4 +-
src/cpu/inorder/resources/fetch_seq_unit.cc | 6 +-
src/cpu/inorder/resources/fetch_unit.cc | 29 +---
src/cpu/inorder/resources/graduation_unit.cc | 4 +-
src/cpu/inorder/resources/inst_buffer.cc | 2 +-
src/cpu/inorder/resources/mult_div_unit.cc | 18 +-
src/cpu/inorder/resources/tlb_unit.cc | 53 +++-----
src/cpu/inorder/resources/tlb_unit.hh | 15 +-
src/cpu/inorder/resources/use_def.cc | 45 ++-----
src/cpu/inorder/resources/use_def.hh | 16 +-
19 files changed, 214 insertions(+), 282 deletions(-)
diffs (truncated from 1097 to 300 lines):
diff -r 143fa8eed0e5 -r de6e9c30ad87 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Fri Feb 18 14:28:22 2011 -0500
+++ b/src/cpu/inorder/cpu.cc Fri Feb 18 14:28:30 2011 -0500
@@ -324,12 +324,7 @@
tid,
asid[tid]);
- dummyReq[tid] = new ResourceRequest(resPool->getResource(0),
- dummyInst[tid],
- 0,
- 0,
- 0,
- 0);
+ dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
}
dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
diff -r 143fa8eed0e5 -r de6e9c30ad87 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Fri Feb 18 14:28:22 2011 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Fri Feb 18 14:28:30 2011 -0500
@@ -938,6 +938,7 @@
"\n", tid, inst->seqNum, cpu->resPool->name(res_num));
ResReqPtr req = cpu->resPool->request(res_num, inst);
+ assert(req->valid);
if (req->isCompleted()) {
DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s "
diff -r 143fa8eed0e5 -r de6e9c30ad87 src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc Fri Feb 18 14:28:22 2011 -0500
+++ b/src/cpu/inorder/resource.cc Fri Feb 18 14:28:30 2011 -0500
@@ -43,7 +43,7 @@
reqs.resize(width);
// Use to deny a instruction a resource.
- deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0);
+ deniedReq = new ResourceRequest(this);
}
Resource::~Resource()
@@ -60,7 +60,7 @@
resourceEvent = new ResourceEvent[width];
for (int i = 0; i < width; i++) {
- reqs[i] = new ResourceRequest(this, NULL, 0, 0, 0, 0);
+ reqs[i] = new ResourceRequest(this);
}
initSlots();
@@ -100,39 +100,28 @@
// Put slot number on this resource's free list
availSlots.push_back(slot_idx);
- // Erase Request Pointer From Request Map
- std::map<int, ResReqPtr>::iterator req_it = reqMap.find(slot_idx);
-
- assert(req_it != reqMap.end());
- reqMap.erase(req_it);
-
+ // Invalidate Request & Reset it's flags
+ reqs[slot_idx]->clearRequest();
}
-// TODO: More efficiently search for instruction's slot within
-// resource.
int
Resource::findSlot(DynInstPtr inst)
{
- map<int, ResReqPtr>::iterator map_it = reqMap.begin();
- map<int, ResReqPtr>::iterator map_end = reqMap.end();
-
int slot_num = -1;
- while (map_it != map_end) {
- if ((*map_it).second->getInst()->seqNum ==
- inst->seqNum) {
- slot_num = (*map_it).second->getSlot();
+ for (int i = 0; i < width; i++) {
+ if (reqs[i]->valid &&
+ reqs[i]->getInst()->seqNum == inst->seqNum) {
+ slot_num = reqs[i]->getSlot();
}
- map_it++;
}
-
return slot_num;
}
int
Resource::getSlot(DynInstPtr inst)
{
- int slot_num;
+ int slot_num = -1;
if (slotsAvail() != 0) {
slot_num = availSlots[0];
@@ -142,24 +131,6 @@
assert(slot_num == *vect_it);
availSlots.erase(vect_it);
- } else {
- DPRINTF(Resource, "[tid:%i]: No slots in resource "
- "available to service [sn:%i].\n", inst->readTid(),
- inst->seqNum);
- slot_num = -1;
-
- map<int, ResReqPtr>::iterator map_it = reqMap.begin();
- map<int, ResReqPtr>::iterator map_end = reqMap.end();
-
- while (map_it != map_end) {
- if ((*map_it).second) {
- DPRINTF(Resource, "Currently Serving request from: "
- "[tid:%i] [sn:%i].\n",
- (*map_it).second->getInst()->readTid(),
- (*map_it).second->getInst()->seqNum);
- }
- map_it++;
- }
}
return slot_num;
@@ -206,7 +177,7 @@
inst->readTid());
}
- reqMap[slot_num] = inst_req;
+ reqs[slot_num] = inst_req;
try_request = true;
}
@@ -242,32 +213,21 @@
Resource::getRequest(DynInstPtr inst, int stage_num, int res_idx,
int slot_num, unsigned cmd)
{
- return new ResourceRequest(this, inst, stage_num, id, slot_num,
- cmd);
+ reqs[slot_num]->setRequest(inst, stage_num, id, slot_num, cmd);
+ return reqs[slot_num];
}
ResReqPtr
Resource::findRequest(DynInstPtr inst)
{
- map<int, ResReqPtr>::iterator map_it = reqMap.begin();
- map<int, ResReqPtr>::iterator map_end = reqMap.end();
-
- bool found = false;
- ResReqPtr req = NULL;
-
- while (map_it != map_end) {
- if ((*map_it).second &&
- (*map_it).second->getInst() == inst) {
- req = (*map_it).second;
- //return (*map_it).second;
- assert(found == false);
- found = true;
+ for (int i = 0; i < width; i++) {
+ if (reqs[i]->valid &&
+ reqs[i]->getInst() == inst) {
+ return reqs[i];
}
- map_it++;
}
- return req;
- //return NULL;
+ return NULL;
}
void
@@ -281,9 +241,9 @@
Resource::execute(int slot_idx)
{
DPRINTF(Resource, "[tid:%i]: Executing %s resource.\n",
- reqMap[slot_idx]->getTid(), name());
- reqMap[slot_idx]->setCompleted(true);
- reqMap[slot_idx]->done();
+ reqs[slot_idx]->getTid(), name());
+ reqs[slot_idx]->setCompleted(true);
+ reqs[slot_idx]->done();
}
void
@@ -299,15 +259,10 @@
Resource::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
ThreadID tid)
{
- std::vector<int> slot_remove_list;
+ for (int i = 0; i < width; i++) {
+ ResReqPtr req_ptr = reqs[i];
- map<int, ResReqPtr>::iterator map_it = reqMap.begin();
- map<int, ResReqPtr>::iterator map_end = reqMap.end();
-
- while (map_it != map_end) {
- ResReqPtr req_ptr = (*map_it).second;
-
- if (req_ptr &&
+ if (req_ptr->valid &&
req_ptr->getInst()->readTid() == tid &&
req_ptr->getInst()->seqNum > squash_seq_num) {
@@ -322,16 +277,8 @@
if (resourceEvent[req_slot_num].scheduled())
unscheduleEvent(req_slot_num);
- // Mark slot for removal from resource
- slot_remove_list.push_back(req_ptr->getSlot());
+ freeSlot(req_slot_num);
}
-
- map_it++;
- }
-
- // Now Delete Slot Entry from Req. Map
- for (int i = 0; i < slot_remove_list.size(); i++) {
- freeSlot(slot_remove_list[i]);
}
}
@@ -366,8 +313,8 @@
Resource::scheduleEvent(int slot_idx, int delay)
{
DPRINTF(Resource, "[tid:%i]: Scheduling event for [sn:%i] on tick %i.\n",
- reqMap[slot_idx]->inst->readTid(),
- reqMap[slot_idx]->inst->seqNum,
+ reqs[slot_idx]->inst->readTid(),
+ reqs[slot_idx]->inst->seqNum,
cpu->ticks(delay) + curTick());
resourceEvent[slot_idx].scheduleEvent(delay);
}
@@ -404,32 +351,10 @@
int ResourceRequest::maxReqCount = 0;
-ResourceRequest::ResourceRequest(Resource *_res, DynInstPtr _inst,
- int stage_num, int res_idx, int slot_num,
- unsigned _cmd)
- : res(_res), inst(_inst), cmd(_cmd), valid(false), stageNum(stage_num),
- resIdx(res_idx), slotNum(slot_num), completed(false),
- squashed(false), processing(false), memStall(false)
+ResourceRequest::ResourceRequest(Resource *_res)
+ : res(_res), inst(NULL), stagePasses(0), valid(false), complSlotNum(-1),
+ completed(false), squashed(false), processing(false), memStall(false)
{
-#ifdef DEBUG
- reqID = resReqID++;
- res->cpu->resReqCount++;
- DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID,
- res->cpu->resReqCount);
-
- if (res->cpu->resReqCount > 100) {
- fatal("Too many undeleted resource requests. Memory leak?\n");
- }
-
- if (res->cpu->resReqCount > maxReqCount) {
- maxReqCount = res->cpu->resReqCount;
- }
-
-#endif
-
- stagePasses = 0;
- complSlotNum = -1;
-
}
ResourceRequest::~ResourceRequest()
@@ -442,6 +367,26 @@
}
void
+ResourceRequest::setRequest(DynInstPtr _inst, int stage_num,
+ int res_idx, int slot_num, unsigned _cmd)
+{
+ valid = true;
+ inst = _inst;
+ stageNum = stage_num;
+ resIdx = res_idx;
+ slotNum = slot_num;
+ cmd = _cmd;
+}
+
+void
+ResourceRequest::clearRequest()
+{
+ valid = false;
+ inst = NULL;
+ stagePasses = 0;
+}
+
+void
ResourceRequest::done(bool completed)
{
DPRINTF(Resource, "%s [slot:%i] done with request from "
diff -r 143fa8eed0e5 -r de6e9c30ad87 src/cpu/inorder/resource.hh
--- a/src/cpu/inorder/resource.hh Fri Feb 18 14:28:22 2011 -0500
+++ b/src/cpu/inorder/resource.hh Fri Feb 18 14:28:30 2011 -0500
@@ -221,9 +221,9 @@
const int latency;
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