changeset 5a0ba3f96300 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5a0ba3f96300
description:
inorder: fix cache/fetch unit memory leaks
---
need to delete the cache request's data on clearRequest() now that we
are recycling
requests
---
fetch unit needs to deallocate the fetch buffer blocks when they are
replaced or
squashed.
diffstat:
src/cpu/inorder/resources/cache_unit.cc | 2 --
src/cpu/inorder/resources/cache_unit.hh | 4 ++++
src/cpu/inorder/resources/fetch_unit.cc | 31 +++++++++++++++++++++++++++++++
src/cpu/inorder/resources/fetch_unit.hh | 2 ++
4 files changed, 37 insertions(+), 2 deletions(-)
diffs (93 lines):
diff -r de10174cd496 -r 5a0ba3f96300 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Fri Feb 18 14:29:02 2011 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Fri Feb 18 14:29:17 2011 -0500
@@ -648,8 +648,6 @@
if (inst->fault == NoFault) {
if (!cache_req->splitAccess) {
- // Remove this line since storeData is saved in INST?
- cache_req->reqData = new uint8_t[size];
doCacheAccess(inst, write_res);
} else {
doCacheAccess(inst, write_res, cache_req);
diff -r de10174cd496 -r 5a0ba3f96300 src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Fri Feb 18 14:29:02 2011 -0500
+++ b/src/cpu/inorder/resources/cache_unit.hh Fri Feb 18 14:29:17 2011 -0500
@@ -249,6 +249,10 @@
void clearRequest()
{
+ if (reqData && !splitAccess) {
+ delete [] reqData;
+ }
+
memReq = NULL;
reqData = NULL;
dataPkt = NULL;
diff -r de10174cd496 -r 5a0ba3f96300 src/cpu/inorder/resources/fetch_unit.cc
--- a/src/cpu/inorder/resources/fetch_unit.cc Fri Feb 18 14:29:02 2011 -0500
+++ b/src/cpu/inorder/resources/fetch_unit.cc Fri Feb 18 14:29:17 2011 -0500
@@ -56,6 +56,31 @@
predecoder(NULL)
{ }
+FetchUnit::~FetchUnit()
+{
+ std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
+ std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
+ while (fetch_it != end_it) {
+ delete (*fetch_it)->block;
+ delete *fetch_it;
+ fetch_it++;
+ }
+ fetchBuffer.clear();
+
+
+ std::list<FetchBlock*>::iterator pend_it = pendingFetch.begin();
+ std::list<FetchBlock*>::iterator pend_end = pendingFetch.end();
+ while (pend_it != pend_end) {
+ if ((*pend_it)->block) {
+ delete (*pend_it)->block;
+ }
+
+ delete *pend_it;
+ pend_it++;
+ }
+ pendingFetch.clear();
+}
+
void
FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
DynInstPtr inst)
@@ -328,6 +353,8 @@
return;
}
+ delete [] (*repl_it)->block;
+ delete *repl_it;
fetchBuffer.erase(repl_it);
}
@@ -506,6 +533,10 @@
DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
"for block %08p (cnt=%i)\n", inst->seqNum,
block_addr, (*block_it)->cnt);
+ if ((*block_it)->block) {
+ delete [] (*block_it)->block;
+ }
+ delete *block_it;
pendingFetch.erase(block_it);
}
}
diff -r de10174cd496 -r 5a0ba3f96300 src/cpu/inorder/resources/fetch_unit.hh
--- a/src/cpu/inorder/resources/fetch_unit.hh Fri Feb 18 14:29:02 2011 -0500
+++ b/src/cpu/inorder/resources/fetch_unit.hh Fri Feb 18 14:29:17 2011 -0500
@@ -55,6 +55,8 @@
FetchUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
+ virtual ~FetchUnit();
+
typedef ThePipeline::DynInstPtr DynInstPtr;
typedef TheISA::ExtMachInst ExtMachInst;
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
