changeset 2c841ed4355e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2c841ed4355e
description:
inorder: cleanup in destructors
cleanup hanging pointers and other cruft in the destructors
diffstat:
src/cpu/inorder/cpu.cc | 13 ++++++++++++-
src/cpu/inorder/cpu.hh | 1 +
src/cpu/inorder/pipeline_stage.cc | 20 ++++++++++++++------
src/cpu/inorder/pipeline_stage.hh | 15 +--------------
src/cpu/inorder/reg_dep_map.cc | 8 ++++++++
src/cpu/inorder/reg_dep_map.hh | 2 +-
src/cpu/inorder/resource.cc | 7 ++++++-
7 files changed, 43 insertions(+), 23 deletions(-)
diffs (174 lines):
diff -r 5a0ba3f96300 -r 2c841ed4355e src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Fri Feb 18 14:29:17 2011 -0500
+++ b/src/cpu/inorder/cpu.cc Fri Feb 18 14:29:26 2011 -0500
@@ -356,6 +356,17 @@
InOrderCPU::~InOrderCPU()
{
delete resPool;
+
+ std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_it =
+ skedCache.begin();
+ std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_end =
+ skedCache.end();
+
+ while (sked_it != sked_end) {
+ delete (*sked_it).second;
+ sked_it++;
+ }
+ skedCache.clear();
}
std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
@@ -460,7 +471,7 @@
W.needs(Grad, GraduationUnit::GraduateInst);
- // Insert Front Schedule into our cache of
+ // Insert Back Schedule into our cache of
// resource schedules
addToSkedCache(inst, res_sked);
diff -r 5a0ba3f96300 -r 2c841ed4355e src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Fri Feb 18 14:29:17 2011 -0500
+++ b/src/cpu/inorder/cpu.hh Fri Feb 18 14:29:26 2011 -0500
@@ -315,6 +315,7 @@
void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
{
SkedID sked_id = genSkedID(inst);
+ assert(skedCache.find(sked_id) == skedCache.end());
skedCache[sked_id] = inst_sked;
}
diff -r 5a0ba3f96300 -r 2c841ed4355e src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Fri Feb 18 14:29:17 2011 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Fri Feb 18 14:29:26 2011 -0500
@@ -44,12 +44,17 @@
stageBufferMax(params->stageWidth),
prevStageValid(false), nextStageValid(false), idle(false)
{
- switchedOutBuffer.resize(ThePipeline::MaxThreads);
- switchedOutValid.resize(ThePipeline::MaxThreads);
-
init(params);
}
+PipelineStage::~PipelineStage()
+{
+ for(ThreadID tid = 0; tid < numThreads; tid++) {
+ skidBuffer[tid].clear();
+ stalls[tid].resources.clear();
+ }
+}
+
void
PipelineStage::init(Params *params)
{
@@ -66,6 +71,12 @@
else
lastStallingStage[tid] = NumStages - 1;
}
+
+ if ((InOrderCPU::ThreadModel) params->threadModel ==
+ InOrderCPU::SwitchOnCacheMiss) {
+ switchedOutBuffer.resize(ThePipeline::MaxThreads);
+ switchedOutValid.resize(ThePipeline::MaxThreads);
+ }
}
@@ -190,9 +201,6 @@
stalls[tid].resources.clear();
- while (!insts[tid].empty())
- insts[tid].pop();
-
skidBuffer[tid].clear();
}
wroteToTimeBuffer = false;
diff -r 5a0ba3f96300 -r 2c841ed4355e src/cpu/inorder/pipeline_stage.hh
--- a/src/cpu/inorder/pipeline_stage.hh Fri Feb 18 14:29:17 2011 -0500
+++ b/src/cpu/inorder/pipeline_stage.hh Fri Feb 18 14:29:26 2011 -0500
@@ -91,10 +91,7 @@
public:
PipelineStage(Params *params, unsigned stage_num);
- /** MUST use init() function if this constructor is used. */
- PipelineStage() { }
-
- virtual ~PipelineStage() { }
+ virtual ~PipelineStage();
/** PipelineStage initialization. */
void init(Params *params);
@@ -268,16 +265,6 @@
*/
unsigned instsProcessed;
- /** Queue of all instructions coming from previous stage on this cycle. */
- std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
-
- /** Queue of instructions that are finished processing and ready to go
- * next stage. This is used to prevent from processing an instrution more
- * than once on any stage. NOTE: It is up to the PROGRAMMER must manage
- * this as a queue
- */
- std::list<DynInstPtr> instsToNextStage;
-
/** Skid buffer between previous stage and this one. */
std::list<DynInstPtr> skidBuffer[ThePipeline::MaxThreads];
diff -r 5a0ba3f96300 -r 2c841ed4355e src/cpu/inorder/reg_dep_map.cc
--- a/src/cpu/inorder/reg_dep_map.cc Fri Feb 18 14:29:17 2011 -0500
+++ b/src/cpu/inorder/reg_dep_map.cc Fri Feb 18 14:29:26 2011 -0500
@@ -45,6 +45,14 @@
regMap.resize(size);
}
+RegDepMap::~RegDepMap()
+{
+ for (int i = 0; i < regMap.size(); i++) {
+ regMap[i].clear();
+ }
+ regMap.clear();
+}
+
string
RegDepMap::name()
{
diff -r 5a0ba3f96300 -r 2c841ed4355e src/cpu/inorder/reg_dep_map.hh
--- a/src/cpu/inorder/reg_dep_map.hh Fri Feb 18 14:29:17 2011 -0500
+++ b/src/cpu/inorder/reg_dep_map.hh Fri Feb 18 14:29:26 2011 -0500
@@ -48,7 +48,7 @@
public:
RegDepMap(int size = TheISA::TotalNumRegs);
- ~RegDepMap() { }
+ ~RegDepMap();
std::string name();
diff -r 5a0ba3f96300 -r 2c841ed4355e src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc Fri Feb 18 14:29:17 2011 -0500
+++ b/src/cpu/inorder/resource.cc Fri Feb 18 14:29:26 2011 -0500
@@ -53,7 +53,11 @@
delete [] resourceEvent;
}
- delete deniedReq;
+ delete deniedReq;
+
+ for (int i = 0; i < width; i++) {
+ delete reqs[i];
+ }
}
@@ -386,6 +390,7 @@
DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID,
res->cpu->resReqCount);
#endif
+ inst = NULL;
}
void
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