changeset ec39f497eadf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ec39f497eadf
description:
inorder: regr-update: reduce dynamic mem. use to speedup sims
previous changesets took a closer look at memory mgmt in the inorder
model and sought to avoid
dynamic memory mgmt (for access to pipeline resources) as much as
possible. For the regressions
that were run, the sims are about 2x speedup from changeset 7726 which
is the last change
since the recent commits in Feb. (note: these regressions now are
4-issue CPUs instead of just 1-issue)
diffstat:
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout | 10 +-
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 212 +++++-----
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout | 10 +-
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 202 ++++----
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout | 10 +-
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 126 ++--
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout | 10 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt | 154 +++---
8 files changed, 367 insertions(+), 367 deletions(-)
diffs (truncated from 1433 to 300 lines):
diff -r 3ae037a196a2 -r ec39f497eadf
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Fri Feb
18 14:31:31 2011 -0500
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Fri Feb
18 14:31:37 2011 -0500
@@ -5,12 +5,12 @@
All Rights Reserved
-M5 compiled Feb 7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Feb 18 2011 15:40:30
+M5 revision Unknown
+M5 started Feb 18 2011 18:53:22
+M5 executing on m55-001.pool
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 43686968500 because halt instruction encountered
+Exiting @ tick 43687852500 because target called exit()
diff -r 3ae037a196a2 -r ec39f497eadf
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Fri Feb
18 14:31:31 2011 -0500
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Fri Feb
18 14:31:37 2011 -0500
@@ -1,25 +1,25 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 106274 #
Simulator instruction rate (inst/s)
-host_mem_usage 1642336 #
Number of bytes of host memory used
-host_seconds 831.26 #
Real time elapsed on the host
-host_tick_rate 52555245 #
Simulator tick rate (ticks/s)
+host_inst_rate 140237 #
Simulator instruction rate (inst/s)
+host_mem_usage 237028 #
Number of bytes of host memory used
+host_seconds 629.94 #
Real time elapsed on the host
+host_tick_rate 69352666 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 88340674 #
Number of instructions simulated
-sim_seconds 0.043687 #
Number of seconds simulated
-sim_ticks 43686968500 #
Number of ticks simulated
+sim_insts 88340673 #
Number of instructions simulated
+sim_seconds 0.043688 #
Number of seconds simulated
+sim_ticks 43687852500 #
Number of ticks simulated
system.cpu.AGEN-Unit.agens 35033051 #
Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct 40.125175 #
BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits 4678518 #
Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups 11659807 #
Number of BTB lookups
+system.cpu.Branch-Predictor.BTBHitPct 40.125186 #
BTB Hit Percentage
+system.cpu.Branch-Predictor.BTBHits 4678520 #
Number of BTB hits
+system.cpu.Branch-Predictor.BTBLookups 11659809 #
Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect 1539 #
Number of incorrect RAS predictions.
system.cpu.Branch-Predictor.condIncorrect 753993 #
Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted 9173158 #
Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups 14237669 #
Number of BP lookups
+system.cpu.Branch-Predictor.condPredicted 9173160 #
Number of conditional branches predicted
+system.cpu.Branch-Predictor.lookups 14237671 #
Number of BP lookups
system.cpu.Branch-Predictor.predictedNotTaken 6139595
# Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 8098074
# Number of Branches Predicted As Taken (True).
+system.cpu.Branch-Predictor.predictedTaken 8098076
# Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 1660495 #
Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions 53620617 #
Number of Instructions Executed.
+system.cpu.Execution-Unit.executions 44841137 #
Number of Instructions Executed.
system.cpu.Execution-Unit.mispredictPct 5.481801 #
Percentage of Incorrect Branches Predicts
system.cpu.Execution-Unit.mispredicted 753993 #
Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted 13000484 #
Number of Branches Incorrectly Predicted
@@ -27,43 +27,43 @@
system.cpu.Execution-Unit.predictedTakenIncorrect 203091
# Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 #
Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 41101 #
Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 145605016
# Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 93058135 #
Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 145605009
# Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 93058128 #
Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 52546881 #
Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 13517269 #
Number of Registers Read Through Forwarding Logic
-system.cpu.activity 70.714707 #
Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 13517276 #
Number of Registers Read Through Forwarding Logic
+system.cpu.activity 70.715162 #
Percentage of cycles cpu is active
system.cpu.comBranches 13754477 #
Number of Branches instructions committed
system.cpu.comFloats 151453 #
Number of Floating Point instructions committed
system.cpu.comInts 30791227 #
Number of Integer instructions committed
system.cpu.comLoads 20276638 #
Number of Load instructions committed
-system.cpu.comNonSpec 4584 #
Number of Non-Speculative instructions committed
+system.cpu.comNonSpec 4583 #
Number of Non-Speculative instructions committed
system.cpu.comNops 8748916 #
Number of Nop instructions committed
system.cpu.comStores 14613377 #
Number of Store instructions committed
-system.cpu.committedInsts 88340674 #
Number of Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 88340674 #
Number of Instructions Simulated (Total)
+system.cpu.committedInsts 88340673 #
Number of Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 88340673 #
Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 #
Number of context switches
-system.cpu.cpi 0.989057 #
CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 0.989057 #
CPI: Total CPI of All Threads
+system.cpu.cpi 0.989077 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 0.989077 #
CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20276638 #
number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 43413.349504
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34421.543297
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34421.526841
# average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20182230 #
number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4098567500 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004656 #
miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 94408 #
number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 33642 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2091659500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2091658500
# number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 #
mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 50157.670646
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49503.458051
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 50157.576620
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49503.360543
# average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14405989 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 10402099000 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 10402079500 #
number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.014192 #
miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 207388 #
number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 63810 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 7107607500
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 7107593500
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143578 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
@@ -75,31 +75,31 @@
system.cpu.dcache.blocked_cycles::no_targets 2727000
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 48047.908190 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 45018.532475
# average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 48047.843576 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 45018.459069
# average overall mshr miss latency
system.cpu.dcache.demand_hits 34588219 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 14500666500 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 14500647000 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.008650 #
miss rate for demand accesses
system.cpu.dcache.demand_misses 301796 #
number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 97452 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9199267000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 9199252000
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005857 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204344 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.994103 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4071.844776 #
Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 4071.844772 #
Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 48047.908190
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 45018.532475
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 48047.843576
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 45018.459069
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34588219 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 14500666500 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 14500647000 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.008650 #
miss rate for overall accesses
system.cpu.dcache.overall_misses 301796 #
number of overall misses
system.cpu.dcache.overall_mshr_hits 97452 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9199267000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 9199252000
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005857 #
mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204344 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -107,9 +107,9 @@
system.cpu.dcache.replacements 200248 #
number of replacements
system.cpu.dcache.sampled_refs 204344 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4071.844776 #
Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4071.844772 #
Cycle average of tags in use
system.cpu.dcache.total_refs 34588219 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 497786000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 497796000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 161214 #
number of writebacks
system.cpu.dtb.data_accesses 34987415 #
DTB accesses
system.cpu.dtb.data_acv 0 #
DTB access violations
@@ -127,51 +127,51 @@
system.cpu.dtb.write_acv 0 #
DTB write access violations
system.cpu.dtb.write_hits 14613377 #
DTB write hits
system.cpu.dtb.write_misses 7252 #
DTB write misses
-system.cpu.icache.ReadReq_accesses 11384473 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18619.899316
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.624423
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 11286741 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1819760000 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 11384439 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 18620.927639
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.720286
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 11286707 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1819860500 #
number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.008585 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 97732 #
number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 9063 #
number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1379479000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 1379487500
# number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.007789 #
mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 88669 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 18115.384615
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 127.292157 #
Average number of references to valid blocks.
+system.cpu.icache.avg_refs 127.291774 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked::no_targets 39 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 706500
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 11384473 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18619.899316 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15557.624423
# average overall mshr miss latency
-system.cpu.icache.demand_hits 11286741 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1819760000 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 11384439 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 18620.927639 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15557.720286
# average overall mshr miss latency
+system.cpu.icache.demand_hits 11286707 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1819860500 #
number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.008585 #
miss rate for demand accesses
system.cpu.icache.demand_misses 97732 #
number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 9063 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1379479000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1379487500
# number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.007789 #
mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 88669 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.918761 #
Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1881.622790 #
Average occupied blocks per context
-system.cpu.icache.overall_accesses 11384473 #
number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18619.899316
# average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15557.624423
# average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.918759 #
Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1881.619179 #
Average occupied blocks per context
+system.cpu.icache.overall_accesses 11384439 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 18620.927639
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15557.720286
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 11286741 #
number of overall hits
-system.cpu.icache.overall_miss_latency 1819760000 #
number of overall miss cycles
+system.cpu.icache.overall_hits 11286707 #
number of overall hits
+system.cpu.icache.overall_miss_latency 1819860500 #
number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.008585 #
miss rate for overall accesses
system.cpu.icache.overall_misses 97732 #
number of overall misses
system.cpu.icache.overall_mshr_hits 9063 #
number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1379479000
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1379487500
# number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.007789 #
mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 88669 #
number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -179,20 +179,20 @@
system.cpu.icache.replacements 86622 #
number of replacements
system.cpu.icache.sampled_refs 88668 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1881.622790 #
Cycle average of tags in use
-system.cpu.icache.total_refs 11286741 #
Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1881.619179 #
Cycle average of tags in use
+system.cpu.icache.total_refs 11286707 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
-system.cpu.idleCycles 25587714 #
Number of cycles cpu's stages were not processed
-system.cpu.ipc 1.011064 #
IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 1.011064 #
IPC: Total IPC of All Threads
+system.cpu.idleCycles 25587834 #
Number of cycles cpu's stages were not processed
+system.cpu.ipc 1.011044 #
IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 1.011044 #
IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 #
DTB accesses
system.cpu.itb.data_acv 0 #
DTB access violations
system.cpu.itb.data_hits 0 #
DTB hits
system.cpu.itb.data_misses 0 #
DTB misses
-system.cpu.itb.fetch_accesses 11389750 #
ITB accesses
+system.cpu.itb.fetch_accesses 11389716 #
ITB accesses
system.cpu.itb.fetch_acv 0 #
ITB acv
-system.cpu.itb.fetch_hits 11384494 #
ITB hits
+system.cpu.itb.fetch_hits 11384460 #
ITB hits
system.cpu.itb.fetch_misses 5256 #
ITB misses
system.cpu.itb.read_accesses 0 #
DTB read accesses
system.cpu.itb.read_acv 0 #
DTB read access violations
@@ -203,23 +203,23 @@
system.cpu.itb.write_hits 0 #
DTB write hits
system.cpu.itb.write_misses 0 #
DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143582 #
number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52040.936228
# average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.851808
# average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52040.829752
# average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.848005
# average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12097 #
number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 6842602500 #
number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 6842588500 #
number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.915748 #
miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 131485 #
number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259512000
# number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259511500
# number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915748
# mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 131485 #
number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 149430 #
number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52294.227145
# average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40025.874305
# average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52294.157340
# average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40025.851037
# average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 106453 #
number of ReadReq hits
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