I apologize for the multiple merges, but I assure you it was not because I was negligent. Instead, it was cause by some technical issues beyond my control.
The merges don't conflict with the same files, so I think the impact should be minimal. Brad > -----Original Message----- > From: [email protected] [mailto:[email protected]] > On Behalf Of Brad Beckmann > Sent: Tuesday, February 22, 2011 11:26 AM > To: [email protected] > Subject: [m5-dev] changeset in m5: m5: merged in hammer fix > > changeset e6ce478c05d3 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=e6ce478c05d3 > description: > m5: merged in hammer fix > > diffstat: > > LICENSE > | 2 +- > README > | 32 +- > RELEASE_NOTES > | 136 - > configs/common/FSConfig.py > | 1 + > src/SConscript > | 2 +- > src/arch/arm/table_walker.cc > | 17 +- > src/arch/arm/table_walker.hh > | 20 +- > src/arch/arm/tlb.cc > | 2 + > src/arch/generic/debugfaults.hh > | 111 + > src/arch/mips/isa/decoder.isa > | 16 +- > src/arch/x86/SConscript > | 1 + > src/arch/x86/insts/badmicroop.cc > | 55 + > src/arch/x86/insts/badmicroop.hh > | 52 + > src/arch/x86/insts/macroop.hh > | 7 +- > src/arch/x86/insts/microregop.cc > | 3 - > src/arch/x86/isa/includes.isa > | 2 + > src/arch/x86/isa/microops/debug.isa > | 69 +- > src/arch/x86/isa/microops/ldstop.isa > | 78 +- > src/arch/x86/isa/microops/limmop.isa > | 27 +- > src/arch/x86/isa/microops/regop.isa > | 293 +- > src/arch/x86/microcode_rom.hh > | 7 +- > src/arch/x86/predecoder.hh > | 6 +- > src/arch/x86/types.hh > | 56 +- > src/base/SConscript > | 1 + > src/base/bitmap.cc > | 82 + > src/base/bitmap.hh > | 114 + > src/base/compiler.hh > | 2 + > src/base/vnc/SConscript > | 48 + > src/base/vnc/VncServer.py > | 45 + > src/base/vnc/convert.cc > | 139 + > src/base/vnc/convert.hh > | 141 + > src/base/vnc/vncserver.cc > | 703 + > src/base/vnc/vncserver.hh > | 475 + > src/cpu/base_dyn_inst.hh > | 125 +- > src/cpu/base_dyn_inst_impl.hh > | 15 + > src/cpu/inorder/SConscript > | 3 +- > src/cpu/inorder/cpu.cc > | 173 +- > src/cpu/inorder/cpu.hh > | 96 +- > src/cpu/inorder/first_stage.cc > | 2 +- > src/cpu/inorder/inorder_dyn_inst.cc > | 30 +- > src/cpu/inorder/inorder_dyn_inst.hh > | 109 +- > src/cpu/inorder/pipeline_stage.cc > | 62 +- > src/cpu/inorder/pipeline_stage.hh > | 15 +- > src/cpu/inorder/pipeline_traits.cc > | 171 - > src/cpu/inorder/pipeline_traits.hh > | 20 +- > src/cpu/inorder/reg_dep_map.cc > | 8 + > src/cpu/inorder/reg_dep_map.hh > | 2 +- > src/cpu/inorder/resource.cc > | 255 +- > src/cpu/inorder/resource.hh > | 33 +- > src/cpu/inorder/resource_pool.cc > | 23 +- > src/cpu/inorder/resource_pool.hh > | 2 + > src/cpu/inorder/resource_sked.cc > | 78 +- > src/cpu/inorder/resource_sked.hh > | 206 +- > src/cpu/inorder/resources/agen_unit.cc > | 4 +- > src/cpu/inorder/resources/branch_predictor.cc > | 2 +- > src/cpu/inorder/resources/cache_unit.cc > | 161 +- > src/cpu/inorder/resources/cache_unit.hh > | 47 +- > src/cpu/inorder/resources/decode_unit.cc > | 11 +- > src/cpu/inorder/resources/execution_unit.cc > | 47 +- > src/cpu/inorder/resources/execution_unit.hh > | 1 + > src/cpu/inorder/resources/fetch_seq_unit.cc > | 8 +- > src/cpu/inorder/resources/fetch_unit.cc > | 71 +- > src/cpu/inorder/resources/fetch_unit.hh > | 2 + > src/cpu/inorder/resources/graduation_unit.cc > | 22 +- > src/cpu/inorder/resources/graduation_unit.hh > | 4 +- > src/cpu/inorder/resources/inst_buffer.cc > | 15 +- > src/cpu/inorder/resources/inst_buffer_new.cc > | 158 - > src/cpu/inorder/resources/inst_buffer_new.hh > | 109 - > src/cpu/inorder/resources/mult_div_unit.cc > | 22 +- > src/cpu/inorder/resources/tlb_unit.cc > | 56 +- > src/cpu/inorder/resources/tlb_unit.hh > | 15 +- > src/cpu/inorder/resources/use_def.cc > | 65 +- > src/cpu/inorder/resources/use_def.hh > | 18 +- > src/cpu/o3/fetch.hh > | 4 + > src/cpu/o3/fetch_impl.hh > | 23 +- > src/cpu/o3/iew_impl.hh > | 21 + > src/cpu/o3/inst_queue.hh > | 28 + > src/cpu/o3/inst_queue_impl.hh > | 53 +- > src/cpu/o3/lsq_unit_impl.hh > | 10 +- > src/cpu/simple/timing.cc > | 12 +- > src/cpu/simple/timing.hh > | 7 + > src/cpu/translation.hh > | 32 +- > src/dev/SConscript > | 1 + > src/dev/arm/RealView.py > | 24 +- > src/dev/arm/amba_device.cc > | 8 + > src/dev/arm/amba_device.hh > | 13 + > src/dev/arm/kmi.cc > | 270 +- > src/dev/arm/kmi.hh > | 101 +- > src/dev/arm/pl111.cc > | 600 +- > src/dev/arm/pl111.hh > | 178 +- > src/dev/arm/rv_ctrl.cc > | 30 + > src/dev/arm/rv_ctrl.hh > | 10 +- > src/dev/arm/timer_sp804.cc > | 6 +- > src/dev/ps2.cc > | 200 + > src/dev/ps2.hh > | 94 + > src/mem/protocol/MESI_CMP_directory-L1cache.sm > | 35 > +- > src/mem/protocol/MOESI_CMP_directory-L1cache.sm > | 55 > +- > src/mem/protocol/MOESI_CMP_token-L1cache.sm > | 35 > +- > src/mem/protocol/MOESI_hammer-cache.sm > | 57 +- > src/mem/ruby/buffers/MessageBuffer.cc > | 3 + > src/mem/ruby/buffers/MessageBuffer.hh > | 6 + > src/mem/ruby/common/Consumer.hh > | 1 + > src/mem/ruby/network/simple/PerfectSwitch.cc > | 285 +- > src/mem/ruby/network/simple/PerfectSwitch.hh > | 2 + > src/mem/ruby/slicc_interface/Message.hh > | 2 + > src/mem/ruby/slicc_interface/NetworkMessage.hh > | 7 + > src/python/m5/main.py > | 9 - > src/sim/root.cc > | 13 +- > src/sim/root.hh > | 17 +- > src/sim/serialize.cc > | 56 +- > src/sim/serialize.hh > | 8 + > src/sim/tlb.hh > | 18 + > system/alpha/console/Makefile > | 60 + > system/alpha/console/console.c > | 1074 ++ > system/alpha/console/dbmentry.S > | 213 + > system/alpha/console/paljtokern.S > | 174 + > system/alpha/console/paljtoslave.S > | 161 + > system/alpha/console/printf.c > | 301 + > system/alpha/h/cserve.h > | 52 + > system/alpha/h/dc21164FromGasSources.h > | 886 ++ > system/alpha/h/ev5_alpha_defs.h > | 314 + > system/alpha/h/ev5_defs.h > | 598 + > system/alpha/h/ev5_impure.h > | 420 + > system/alpha/h/ev5_osfalpha_defs.h > | 152 + > system/alpha/h/ev5_paldef.h > | 162 + > system/alpha/h/fromHudsonMacros.h > | 88 + > system/alpha/h/fromHudsonOsf.h > | 483 + > system/alpha/h/rpb.h > | 387 + > system/alpha/h/tlaser.h > | 34 + > system/alpha/palcode/Makefile > | 92 + > system/alpha/palcode/osfpal.S > | 4202 ++++++++++ > system/alpha/palcode/platform.S > | 2337 +++++ > tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini > | 2 +- > tests/long/00.gzip/ref/x86/linux/o3-timing/simout > | 10 +- > tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt > | 736 +- > tests/long/00.gzip/ref/x86/linux/simple-atomic/simout > | 6 +- > tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt > | 10 +- > tests/long/00.gzip/ref/x86/linux/simple-timing/simout > | 6 +- > tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt > | 10 +- > tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout > | > 9 +- > tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt > | > 10 +- > tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout > | > 9 +- > tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt > | > 10 +- > tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini > | 2 +- > tests/long/10.mcf/ref/x86/linux/o3-timing/simout > | 10 +- > tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt > | 749 +- > tests/long/10.mcf/ref/x86/linux/simple-atomic/simout > | 6 +- > tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt > | 10 +- > tests/long/10.mcf/ref/x86/linux/simple-timing/simout > | 6 +- > tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt > | 10 +- > tests/long/20.parser/ref/x86/linux/o3-timing/config.ini > | 2 +- > tests/long/20.parser/ref/x86/linux/o3-timing/simout > | 14 +- > tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt > | 774 +- > tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini > | 2 > +- > tests/long/20.parser/ref/x86/linux/simple-atomic/simout > | 8 > +- > tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt > | 10 > +- > tests/long/20.parser/ref/x86/linux/simple-timing/config.ini > | 2 +- > tests/long/20.parser/ref/x86/linux/simple-timing/simout > | 8 +- > tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt > | 10 > +- > tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout > | 10 > +- > tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt > | > 212 +- > tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout > | 6 +- > tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt > | 10 +- > tests/long/60.bzip2/ref/x86/linux/simple-timing/simout > | 6 +- > tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt > | 10 +- > tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout > | 10 > +- > tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt > | 202 > +- > tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini > | 2 +- > tests/long/70.twolf/ref/x86/linux/o3-timing/simout > | 12 +- > tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt > | 719 +- > tests/long/70.twolf/ref/x86/linux/simple-atomic/simout > | 8 +- > tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt > | 10 +- > tests/long/70.twolf/ref/x86/linux/simple-timing/simout > | 8 +- > tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt > | 10 +- > tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout > | 10 > +- > tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt > | 126 > +- > tests/quick/00.hello/ref/mips/linux/inorder-timing/simout > | 10 > +- > tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt > | 154 > +- > tests/quick/00.hello/ref/x86/linux/o3-timing/simout > | 11 +- > tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt > | 684 +- > tests/quick/00.hello/ref/x86/linux/simple-atomic/simout > | 6 +- > tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt > | 10 > +- > tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats > | > 18 +- > tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout > | 6 > +- > tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt > | 10 > +- > tests/quick/00.hello/ref/x86/linux/simple-timing/simout > | 6 +- > tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt > | 8 +- > tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini > | 44 +- > tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr > | 2 + > tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout > | 12 +- > tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt > | 340 +- > tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini > | 44 +- > tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr > | 2 + > tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout > | 12 +- > tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt > | 526 +- > tests/quick/10.linux-boot/ref/arm/linux/realview-simple- > timing/system.terminal | 0 > util/make_release.py > | 222 - > 197 files changed, 20275 insertions(+), 5199 deletions(-) > > diffs (truncated from 31444 to 300 lines): > > diff -r 43a279c3cde2 -r e6ce478c05d3 LICENSE > --- a/LICENSE Thu Feb 10 13:31:52 2011 -0800 > +++ b/LICENSE Tue Feb 22 11:16:40 2011 -0800 > @@ -1,4 +1,4 @@ > -Copyright (c) 2000-2008 The Regents of The University of Michigan > +Copyright (c) 2000-2011 The Regents of The University of Michigan > All rights reserved. > > Redistribution and use in source and binary forms, with or without diff -r > 43a279c3cde2 -r e6ce478c05d3 README > --- a/README Thu Feb 10 13:31:52 2011 -0800 > +++ b/README Tue Feb 22 11:16:40 2011 -0800 > @@ -1,4 +1,4 @@ > -This is release 2.0_beta6 of the M5 simulator. > +This is the M5 simulator. > > For detailed information about building the simulator and getting started > please refer to http://www.m5sim.org. > @@ -9,13 +9,16 @@ > > Short version: > > -1. If you don't have SCons version 0.96.91 or newer, get it from > +1. If you don't have SCons version 0.98.1 or newer, get it from > http://wwww.scons.org. > > -2. If you don't have SWIG version 1.3.28 or newer, get it from > +2. If you don't have SWIG version 1.3.31 or newer, get it from > http://wwww.swig.org. > > -3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This > +3. Make sure you also have gcc version 3.4.6 or newer, Python 2.4 or > +newer (the dev version with header files), zlib, and the m4 preprocessor. > + > +4. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. > +This > will build the debug version of the m5 binary (m5.debug) for the Alpha > syscall emulation target, and run the quick regression tests on it. > > @@ -25,18 +28,21 @@ > ------------------------- > > The basic source release includes these subdirectories: > - - m5: > + - m5: > + - configs: simulation configuration scripts > + - ext: less-common external packages needed to build m5 > - src: source code of the m5 simulator > + - system: source for some optional system software for simulated > + systems > - tests: regression tests > - - ext: less-common external packages needed to build m5 > + - util: useful utility programs and files > > -To run full-system simulations, you will need compiled console, -PALcode, > and kernel binaries and one or more disk images. These files -are collected > in > a separate archive, m5_system.tar.bz2. This file -can he downloaded > separately. > +To run full-system simulations, you will need compiled system firmware > +(console and PALcode for Alpha), kernel binaries and one or more disk > images. > +These files for Alpha are collected in a separate archive, m5_system.tar.bz2. > +This file can he downloaded separately. > > -M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP > -Tru64 version of Unix. We are able to distribute Linux and FreeBSD - > bootdisks, but we are unable to distribute bootable disk images of > +Depending on the ISA used, M5 may support Linux 2.4/2.6, FreeBSD, and > +the proprietary Compaq/HP Tru64 version of Unix. We are able to > +distribute Linux and FreeBSD bootdisks, but we are unable to distribute > +bootable disk images of > Tru64 Unix. If you have a Tru64 license and are interested in obtaining disk > images, contact us at [email protected] diff -r 43a279c3cde2 -r > e6ce478c05d3 RELEASE_NOTES > --- a/RELEASE_NOTES Thu Feb 10 13:31:52 2011 -0800 > +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 > @@ -1,149 +0,0 @@ > -October 6, 2008: m5_2.0_beta6 > --------------------- > -New Features > -1. Support for gcc 4.3 > -2. Core m5 code in libm5 for integration with other simulators -3. > Preliminary > support for X86 SE mode -4. Additional system calls emulated -5. m5term > updated to work on OS X -6. Ability to disable listen sockets -7. Event queue > performance improvements and rewrite -8. Better errors for unconnected > memory ports > - > -Bug fixes > -1. ALPHA_SE O3 perlbmk benchmark > -2. Translation bug where O3 could fetch from uncachable memory -3. Many > minor bugs > - > -Outstanding issues for 2.0 release: > --------------------- > -1. Statistics cleanup > -2. Improve regression system > -3. Testing > -4. Validation > - > -March 1, 2008: m5_2.0_beta5 > --------------------- > -New Features > -1. Rick Strong's Simpoints config changes -2. Support for FSU ARM port -3. > EXTRAS= option allow architectures to be specified > - > -Bug fixes > -1. Bus timing more realistic > -2. Cache writeback, LL/SC fixes > -3. Minor IGbE NIC fixes > -4. O3 op latency fix > -5. SPARC TLB demap fixes > -6. SPARC SE memory layout fixes > -7. Variety of MIPS fixes > - > -Nov 4, 2007: m5_2.0_beta4 > --------------------- > -New Features > -1. New cache model > -2. Use of a I/O cache between devices and memory -3. Ability to include > compiled code with EXTRAS= -4. Python creation of params structures for > initialization -5. Ability to remotely debug in SE > - > -Bug fixes: > -1. Fix SE serialization > -2. SPARC_FS booting with TimingSimpleCPU -3. Rename cycles() to ticks() -4. > Various SPARC ISA fixes -5. Draining code for checkpointing -6. Various > performance improvements > - > -Possible Incompatibilities: > -1. Real TLBs are now used in SE mode. This is more accurate however it could > - cause some problems if you've modified the way page handling is done in > - SE mode. > -2. There have been many changes to the way the SCons files work. > SimObjects, > - sources files, and trace flags are all specified in the SConscript files. > - To see how to add your sources take a look at one of them. > -3. Python is now used to created the parameter structs that were created > - manually before. The parameters listed in a py file are turned into > - a header file with the same name (e.g. BadDevice.py -> BadDevice.hh). > - With this change the structs can be populated automatically and the > - ugly macros to define and create SimObjects at the bottem of source > - files are gone. The parameter structs also automatically inherit > - parameters from their parents. > - > -May 16, 2007: m5_2.0_beta3 > --------------------- > -New Features > -1. Some support for SPARC full-system simulation -2. Reworking of trace > facitities (parameter names changed, variadic macros > - removed) > -3. Scons script cleanups > -4. Some support for compiling with Intel CC > - > -Bug fixes since beta 2: > -1. Many SPARC linux syscall emulation support fixes -2. Multiprocessor linux > boot using the detailed O3 CPU module -3. Workaround for DMA bug (final > solution to be released with 2.0f) -4. Simulator performance and memory > leak fixes -5. Fixed issue where console could stop printing in ALPHA_FS -6. > Fix issues with remote debugging -7. Several compile fixes, including gcc 4.1 > - > 8. Many other minor fixes and enhancements > - > -Nov. 28, 2006: m5_2.0_beta2 > --------------------- > -Bug fixes since beta 1: > -1. Many cache issues resolved > -2. Uni-coherence fixes in full-system > -3. LL/SC Support > -4. Draining/Switchover > -5. Functional Accesses > -6. Bus now has real timing > -7. Single config file for all SpecCPU2000 benchmarks -8. Several other minor > bug fixes and enhancements > - > -Aug. 25, 2006: m5_2.0_beta patch 1 > --------------------- > -Handful of minor bug fixes for m5_2.0_beta, -along with a few new > regression tests. > - > -Aug. 15, 2006: m5_2.0_beta > --------------------- > -Major update to M5 including: > -- New CPU model > -- New memory system > -- More extensive python integration > -- Preliminary syscall emulation support for MIPS and SPARC -This is a *beta* > release, meaning that some features are not complete, -and some features > from M5 1.X aren't currently supported (e.g., MP -coherence). We are > working to address these limitations and hope to -have a complete 2.0 > release soon. > - > -Oct. 8, 2005: m5_1.1 > --------------------- > -Update release for IOSCA workshop mini-tutorial. New features include: > -- Preliminary FreeBSD support > -- Integration of regression tests into scons build framework > -- Several bug fixes and better compatibility for Cygwin hosts > -- Major cleanup of Alpha system code (console, PAL, etc.) to make > - it easier for others to build/modify > -- Fixes to enable compilation under g++ 4.0 > -- Numerous minor bug fixes > - > -June 10, 2005: m5_1.0_web > -------------------------- > -The 1.0 release posted on Sourceforge after the ISCA tutorial contains -just > a > few very minor fixes relative to the CD. > - > -June 5, 2005: m5_1.0_tutorial > ------------------------------ > -First non-beta release. This release was on the CD distributed at the -ISCA > tutorial. Major enhancements relative to beta releases include -Linux > support and Python-based configuration language. > - > -June 17, 2004: m5_1.0_beta2 > ---------------------------- > -Stealth-mode beta bug-fix update, not widely advertised. > - > -Oct. 17, 2003: m5_1.0_beta1 > ---------------------------- > -Early beta release. > diff -r 43a279c3cde2 -r e6ce478c05d3 configs/common/FSConfig.py > --- a/configs/common/FSConfig.py Thu Feb 10 13:31:52 2011 -0800 > +++ b/configs/common/FSConfig.py Tue Feb 22 11:16:40 2011 -0800 > @@ -238,6 +238,7 @@ > > self.intrctrl = IntrControl() > self.terminal = Terminal() > + self.vncserver = VncServer() > self.kernel = binary('vmlinux.arm') > self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 > lpj=19988480' + \ > ' norandmaps slram=slram0,0x8000000,+0x8000000' + > \ > diff -r 43a279c3cde2 -r e6ce478c05d3 src/SConscript > --- a/src/SConscript Thu Feb 10 13:31:52 2011 -0800 > +++ b/src/SConscript Tue Feb 22 11:16:40 2011 -0800 > @@ -446,7 +446,7 @@ > > # Generate a file that wraps the basic top level files > env.Command('python/m5/info.py', > - [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ], > + [ '#/AUTHORS', '#/LICENSE', '#/README', ], > MakeAction(makeInfoPyFile, Transform("INFO"))) PySource('m5', > 'python/m5/info.py') > > diff -r 43a279c3cde2 -r e6ce478c05d3 src/arch/arm/table_walker.cc > --- a/src/arch/arm/table_walker.cc Thu Feb 10 13:31:52 2011 -0800 > +++ b/src/arch/arm/table_walker.cc Tue Feb 22 11:16:40 2011 -0800 > @@ -208,19 +208,20 @@ > return f; > } > > + Request::Flags flag = 0; > + if (currState->sctlr.c == 0) { > + flag = Request::UNCACHEABLE; > + } > + > if (currState->timing) { > port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), > &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, > - currState->tc->getCpuPtr()->ticks(1)); > + currState->tc->getCpuPtr()->ticks(1), flag); > DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: > %d\n", > stateQueueL1.size()); > stateQueueL1.push_back(currState); > currState = NULL; > } else { > - Request::Flags flag = 0; > - if (currState->sctlr.c == 0){ > - flag = Request::UNCACHEABLE; > - } > port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), > NULL, (uint8_t*)&currState->l1Desc.data, > currState->tc->getCpuPtr()->ticks(1), flag); @@ -472,7 > +473,7 @@ > switch (currState->l1Desc.type()) { > case L1Descriptor::Ignore: > case L1Descriptor::Reserved: > - if (!currState->delayed) { > + if (!currState->timing) { > currState->tc = NULL; > currState->req = NULL; > } > @@ -577,7 +578,7 @@ > > if (currState->l2Desc.invalid()) { > DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); > - if (!currState->delayed) { > + if (!currState->timing) { > currState->tc = NULL; > currState->req = NULL; > } > @@ -622,7 +623,7 @@ > memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), > currState->l2Desc.shareable()); > > - if (!currState->delayed) { > + if (!currState->timing) { > currState->tc = NULL; > currState->req = NULL; > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
