changeset a259ab86cabf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a259ab86cabf
description:
ARM: Adds dummy support for a L2 latency miscreg.
diffstat:
src/arch/arm/isa/formats/misc.isa | 3 +++
src/arch/arm/miscregs.cc | 2 ++
src/arch/arm/miscregs.hh | 1 +
3 files changed, 6 insertions(+), 0 deletions(-)
diffs (36 lines):
diff -r 5a8208fa1600 -r a259ab86cabf src/arch/arm/isa/formats/misc.isa
--- a/src/arch/arm/isa/formats/misc.isa Wed Feb 23 14:26:55 2011 -0500
+++ b/src/arch/arm/isa/formats/misc.isa Wed Feb 23 15:10:48 2011 -0600
@@ -143,6 +143,9 @@
case MISCREG_BPIALL:
return new WarnUnimplemented(
isRead ? "mrc bpiall" : "mcr bpiall", machInst);
+ case MISCREG_L2LATENCY:
+ return new WarnUnimplemented(
+ isRead ? "mrc l2latency" : "mcr l2latency", machInst);
// Write only.
case MISCREG_TLBIALLIS:
diff -r 5a8208fa1600 -r a259ab86cabf src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Wed Feb 23 14:26:55 2011 -0500
+++ b/src/arch/arm/miscregs.cc Wed Feb 23 15:10:48 2011 -0600
@@ -381,6 +381,8 @@
return MISCREG_PMINTENCLR;
}
}
+ } else if (opc1 == 1) {
+ return MISCREG_L2LATENCY;
}
//Reserved for Branch Predictor, Cache and TCM operations
break;
diff -r 5a8208fa1600 -r a259ab86cabf src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Wed Feb 23 14:26:55 2011 -0500
+++ b/src/arch/arm/miscregs.hh Wed Feb 23 15:10:48 2011 -0600
@@ -191,6 +191,7 @@
MISCREG_MVBAR,
MISCREG_ISR,
MISCREG_FCEIDR,
+ MISCREG_L2LATENCY,
MISCREG_CP15_END,
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