changeset a3f5f75db279 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a3f5f75db279
description:
ARM: Mark store conditionals as such.
diffstat:
src/arch/arm/isa/insts/str.isa | 9 ++++++---
src/arch/arm/isa/insts/swap.isa | 13 +++++++------
2 files changed, 13 insertions(+), 9 deletions(-)
diffs (98 lines):
diff -r 749581c26e71 -r a3f5f75db279 src/arch/arm/isa/insts/str.isa
--- a/src/arch/arm/isa/insts/str.isa Wed Feb 23 15:10:49 2011 -0600
+++ b/src/arch/arm/isa/insts/str.isa Wed Feb 23 15:10:49 2011 -0600
@@ -47,7 +47,8 @@
execBase = 'Store'
def __init__(self, mnem, post, add, writeback, size=4,
- sign=False, user=False, flavor="normal"):
+ sign=False, user=False, flavor="normal",
+ instFlags = []):
super(StoreInst, self).__init__()
self.name = mnem
@@ -58,7 +59,7 @@
self.sign = sign
self.user = user
self.flavor = flavor
-
+ self.instFlags = instFlags
if self.add:
self.op = " +"
else:
@@ -76,7 +77,7 @@
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
- self.memFlags, [], base, wbDecl)
+ self.memFlags, self.instFlags,
base, wbDecl)
header_output += newHeader
decoder_output += newDecoder
@@ -221,6 +222,7 @@
decConstBase = 'StoreExImm'
basePrefix = 'MemoryExImm'
nameFunc = staticmethod(storeImmClassName)
+ instFlags = ['IsStoreConditional']
def __init__(self, *args, **kargs):
super(StoreImmEx, self).__init__(*args, **kargs)
@@ -300,6 +302,7 @@
decConstBase = 'StoreExDImm'
basePrefix = 'MemoryExDImm'
nameFunc = staticmethod(storeDoubleImmClassName)
+ instFlags = ['IsStoreConditional']
def __init__(self, *args, **kargs):
super(StoreDoubleImmEx, self).__init__(*args, **kargs)
diff -r 749581c26e71 -r a3f5f75db279 src/arch/arm/isa/insts/swap.isa
--- a/src/arch/arm/isa/insts/swap.isa Wed Feb 23 15:10:49 2011 -0600
+++ b/src/arch/arm/isa/insts/swap.isa Wed Feb 23 15:10:49 2011 -0600
@@ -46,7 +46,7 @@
decConstBase = 'Swap'
def __init__(self, name, Name, eaCode,
- preAccCode, postAccCode, memFlags):
+ preAccCode, postAccCode, memFlags, instFlags = []):
super(SwapInst, self).__init__()
self.name = name
self.Name = Name
@@ -54,6 +54,7 @@
self.preAccCode = preAccCode
self.postAccCode = postAccCode
self.memFlags = memFlags
+ self.instFlags = instFlags
def emit(self):
global header_output, decoder_output, exec_output
@@ -61,12 +62,10 @@
"preacc_code": self.preAccCode,
"postacc_code": self.postAccCode }
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
-
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
- self.memFlags,
- ['IsStoreConditional'],
+ self.memFlags, self.instFlags,
base = 'Swap')
header_output += newHeader
decoder_output += newDecoder
@@ -77,12 +76,14 @@
'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP',
'ArmISA::TLB::AlignWord',
- 'ArmISA::TLB::MustBeOne']).emit()
+ 'ArmISA::TLB::MustBeOne'],
+ ['IsStoreConditional']).emit()
SwapInst('swpb', 'Swpb', 'EA = Base;',
'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP',
'ArmISA::TLB::AlignByte',
- 'ArmISA::TLB::MustBeOne']).emit()
+ 'ArmISA::TLB::MustBeOne'],
+ ['IsStoreConditional']).emit()
}};
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