changeset 5651f447e601 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5651f447e601
description:
inorder: bzip2 regression update
diffstat:
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout | 10 +-
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 348 +++++-----
2 files changed, 178 insertions(+), 180 deletions(-)
diffs (truncated from 489 to 300 lines):
diff -r baf4b5f6782e -r 5651f447e601
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout Sat Feb 26
21:43:11 2011 -0800
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout Sun Feb 27
14:17:26 2011 -0500
@@ -7,10 +7,10 @@
All Rights Reserved
-M5 compiled Feb 23 2011 12:26:45
-M5 revision Unknown
-M5 started Feb 23 2011 14:50:29
-M5 executing on m55-001.pool
+M5 compiled Feb 27 2011 03:06:45
+M5 revision baf4b5f6782e 8094 default tip
+M5 started Feb 27 2011 03:13:10
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -30,4 +30,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 916989799500 because target called exit()
+Exiting @ tick 979951369500 because target called exit()
diff -r baf4b5f6782e -r 5651f447e601
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt Sat Feb
26 21:43:11 2011 -0800
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt Sun Feb
27 14:17:26 2011 -0500
@@ -1,38 +1,37 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 136726 #
Simulator instruction rate (inst/s)
-host_mem_usage 444148 #
Number of bytes of host memory used
-host_seconds 13309.73 #
Real time elapsed on the host
-host_tick_rate 68896185 #
Simulator tick rate (ticks/s)
+host_inst_rate 121455 #
Simulator instruction rate (inst/s)
+host_mem_usage 1130520 #
Number of bytes of host memory used
+host_seconds 14983.11 #
Real time elapsed on the host
+host_tick_rate 65403738 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 1819780127 #
Number of instructions simulated
-sim_seconds 0.916990 #
Number of seconds simulated
-sim_ticks 916989799500 #
Number of ticks simulated
-system.cpu.AGEN-Unit.agens 608310443 #
Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct 99.483708 #
BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits 174550225 #
Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups 175456091 #
Number of BTB lookups
-system.cpu.Branch-Predictor.BTBNoTargets 905866 #
Number of times BTB has no targets for prediction
+sim_seconds 0.979951 #
Number of seconds simulated
+sim_ticks 979951369500 #
Number of ticks simulated
+system.cpu.AGEN-Unit.agens 614316005 #
Number of Address Generations
+system.cpu.Branch-Predictor.BTBHitPct 69.872947 #
BTB Hit Percentage
+system.cpu.Branch-Predictor.BTBHits 82064192 #
Number of BTB hits
+system.cpu.Branch-Predictor.BTBLookups 117447733 #
Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect 6 #
Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect 24019275 #
Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted 170526345 #
Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups 223585344 #
Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken 14030167
# Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 209555177
# Number of Branches Predicted As Taken (True).
+system.cpu.Branch-Predictor.condIncorrect 79224651 #
Number of conditional branches incorrect
+system.cpu.Branch-Predictor.condPredicted 175157411 #
Number of conditional branches predicted
+system.cpu.Branch-Predictor.lookups 253574750 #
Number of BP lookups
+system.cpu.Branch-Predictor.predictedNotTaken 124923988
# Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 128650762
# Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 16767439 #
Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions 1139770293 #
Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct 0.000000 #
Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted 0 #
Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predicted 214632552 #
Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect 0
# Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect 0
# Number of Branches Incorrectly Predicted As Taken.
+system.cpu.Execution-Unit.executions 1162207758 #
Number of Instructions Executed.
+system.cpu.Execution-Unit.mispredictPct 36.911759 #
Percentage of Incorrect Branches Predicts
+system.cpu.Execution-Unit.mispredicted 79224651 #
Number of Branches Incorrectly Predicted
+system.cpu.Execution-Unit.predicted 135407901 #
Number of Branches Incorrectly Predicted
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 71572967
# Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect 7651684
# Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 #
Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 75 #
Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 3140255317
# Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 1764052354 #
Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 3178023708
# Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 1801820745 #
Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 1376202963 #
Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 594574228 #
Number of Registers Read Through Forwarding Logic
-system.cpu.activity 72.616672 #
Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 604786987 #
Number of Registers Read Through Forwarding Logic
+system.cpu.activity 74.309805 #
Percentage of cycles cpu is active
system.cpu.comBranches 214632552 #
Number of Branches instructions committed
system.cpu.comFloats 190 #
Number of Floating Point instructions committed
system.cpu.comInts 916086844 #
Number of Integer instructions committed
@@ -43,64 +42,64 @@
system.cpu.committedInsts 1819780127 #
Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 1819780127 #
Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 #
Number of context switches
-system.cpu.cpi 1.007803 #
CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 1.007803 #
CPI: Total CPI of All Threads
+system.cpu.cpi 1.077000 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 1.077000 #
CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 444595663 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24796.654504
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21698.597252
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24782.275660
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21696.910468
# average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 437273551 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 181563881500 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 181458598000 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.016469 #
miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7322112 #
number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 99789 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 156714278000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 156702095500
# number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 #
mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222323 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 36157.228714
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30862.553458
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 158603359 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 76839281500 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 36133.458705
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30848.973440
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 158603354 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 76788947500 #
number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.013222 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2125143 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 235823 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 58309239500
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses 2125148 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 235828 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 58283582500
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1889320 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 15143.435981
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 65.397307 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles::no_targets 15086.569579
# average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 65.397306 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 617 #
number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 618 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 9343500
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 9323500
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
system.cpu.dcache.demand_accesses 605324165 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27352.195214 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23598.764515
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 595876910 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 258403163000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 27335.708502 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23594.611641
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 595876905 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 258247545500 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.015607 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 9447255 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 335612 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 215023517500
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_misses 9447260 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 335617 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 214985678000
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.015053 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9111643 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.996936 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4083.451788 #
Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.996505 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4081.685602 #
Average occupied blocks per context
system.cpu.dcache.overall_accesses 605324165 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27352.195214
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23598.764515
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 27335.708502
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23594.611641
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 595876910 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 258403163000 #
number of overall miss cycles
+system.cpu.dcache.overall_hits 595876905 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 258247545500 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.015607 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 9447255 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 335612 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 215023517500
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_misses 9447260 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 335617 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 214985678000
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.015053 #
mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9111643 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -108,10 +107,10 @@
system.cpu.dcache.replacements 9107547 #
number of replacements
system.cpu.dcache.sampled_refs 9111643 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4083.451788 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 595876910 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 10305899000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 3058779 #
number of writebacks
+system.cpu.dcache.tagsinuse 4081.685602 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 595876905 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 12696089000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 3058780 #
number of writebacks
system.cpu.dtb.data_accesses 611922547 #
DTB accesses
system.cpu.dtb.data_acv 0 #
DTB access violations
system.cpu.dtb.data_hits 605324165 #
DTB hits
@@ -128,72 +127,72 @@
system.cpu.dtb.write_acv 0 #
DTB write access violations
system.cpu.dtb.write_hits 160728502 #
DTB write hits
system.cpu.dtb.write_misses 1701304 #
DTB write misses
-system.cpu.icache.ReadReq_accesses 191269984 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54726.299694
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53438.323353
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 191269003 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 53686500 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 207004701 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 54777.453839
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53438.372093
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 207003672 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 56366000 #
number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000005 #
miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 981 #
number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 146 #
number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 44621000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 1029 #
number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 169 #
number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 45957000
# number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 #
mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 835 #
number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 860 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 20857.142857
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 229064.674251 #
Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles::no_targets 23666.666667
# average number of cycles each access was blocked
+system.cpu.icache.avg_refs 240701.944186 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 7 #
number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 6 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 146000
# number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 142000
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 191269984 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 54726.299694 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53438.323353
# average overall mshr miss latency
-system.cpu.icache.demand_hits 191269003 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 53686500 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 207004701 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 54777.453839 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53438.372093
# average overall mshr miss latency
+system.cpu.icache.demand_hits 207003672 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 56366000 #
number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000005 #
miss rate for demand accesses
-system.cpu.icache.demand_misses 981 #
number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 146 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 44621000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 1029 #
number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 169 #
number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 45957000
# number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 #
mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 835 #
number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 860 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.313093 #
Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 641.213768 #
Average occupied blocks per context
-system.cpu.icache.overall_accesses 191269984 #
number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 54726.299694
# average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53438.323353
# average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.324416 #
Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 664.403935 #
Average occupied blocks per context
+system.cpu.icache.overall_accesses 207004701 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 54777.453839
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53438.372093
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 191269003 #
number of overall hits
-system.cpu.icache.overall_miss_latency 53686500 #
number of overall miss cycles
+system.cpu.icache.overall_hits 207003672 #
number of overall hits
+system.cpu.icache.overall_miss_latency 56366000 #
number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000005 #
miss rate for overall accesses
-system.cpu.icache.overall_misses 981 #
number of overall misses
-system.cpu.icache.overall_mshr_hits 146 #
number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 44621000
# number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 1029 #
number of overall misses
+system.cpu.icache.overall_mshr_hits 169 #
number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 45957000
# number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 #
mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 835 #
number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 860 #
number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 #
number of replacements
-system.cpu.icache.sampled_refs 835 #
Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 860 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 641.213768 #
Cycle average of tags in use
-system.cpu.icache.total_refs 191269003 #
Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 664.403935 #
Cycle average of tags in use
+system.cpu.icache.total_refs 207003672 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
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