changeset 77ee9ad2e113 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=77ee9ad2e113
description:
X86: Mark prefetches as such in their instruction and request flags.
diffstat:
src/arch/x86/isa/microops/ldstop.isa | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diffs (23 lines):
diff -r 2e1ee8ec6266 -r 77ee9ad2e113 src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa Tue Mar 01 15:26:11 2011 -0600
+++ b/src/arch/x86/isa/microops/ldstop.isa Tue Mar 01 22:42:18 2011 -0800
@@ -282,8 +282,10 @@
self.memFlags = baseFlags
if atCPL0:
self.memFlags += " | (CPL0FlagBit << FlagShift)"
+ self.instFlags = ""
if prefetch:
self.memFlags += " | Request::PREFETCH"
+ self.instFlags += " | StaticInst::IsDataPrefetch"
self.memFlags += " | (machInst.legacy.addr ? " + \
"(AddrSizeFlagBit << FlagShift) : 0)"
@@ -293,7 +295,7 @@
%(disp)s, %(segment)s, %(data)s,
%(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
"class_name" : self.className,
- "flags" : self.microFlagsText(microFlags),
+ "flags" : self.microFlagsText(microFlags) + self.instFlags,
"scale" : self.scale, "index" : self.index,
"base" : self.base,
"disp" : self.disp,
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