> On 2011-03-03 16:52:42, Brad Beckmann wrote: > > Do you have to always call wakeUpAllDependents? Initially it atleast was > > my hope that the per cache block wakeUpDependents would be sufficient. > > However, I could see that in certain situations where requets are stalled > > because a tbe entry is unavailable that the per address wakeUpDependents > > could lead to starvation. Do you think we should just elimiate > > wakeUpDependents and just use wakeUpAllDependents?
Brad, I also thought that stalling on cache block basis should be sufficient. In fact my initial code used wakeUpDependents() only. But that did not work out, and I was not able to figure out why that might be the case. And then I thought that stalling requests on a particular address might not be correct. Let me pose this question to you, is stalling on an address same as stalling on a cache block? If it is, then certainly I do not see the need for wakeUpAllDependents(), at least not in the MESI L1 cache controller. But in case the two are not same, then I think we would need to wake up all requests whenever there is a transition from a transient to a stable state. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/330/#review928 ----------------------------------------------------------- On 2011-03-03 09:20:38, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/330/ > ----------------------------------------------------------- > > (Updated 2011-03-03 09:20:38) > > > Review request for Default. > > > Summary > ------- > > This patch adds the stall and wait on the mandatory queue of L1 cache > controller of the MESI CMP directory protocol. It is intended to be > more of a discussion (so as to improve my understanding). > > > Diffs > ----- > > src/cpu/testers/rubytest/RubyTester.py 92229cb0cee9 > src/mem/protocol/MESI_CMP_directory-L1cache.sm 92229cb0cee9 > > Diff: http://reviews.m5sim.org/r/330/diff > > > Testing > ------- > > The changes have been tested for 16 processors for 40 different random > seeds with number of loads varying from a 1,000,000 - 4,000,000. The only > concern is that I had to change the dead lock threshold in RubyTester.py > which is surprising. > > > Thanks, > > Nilay > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
