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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan Binkert, and Brad Beckmann. Summary ------- MOESI_hammer: adding cache flushing This patch adds cache flushing to MOESI_hammer. In order to flush a cache line, a FLUSH request is issued. Flushing is basically a store to a line (with no change to data) followed by a write back to the memory (invalidation). At the L1 cache, up on a flush request, a GETF (similar to GETX) is issued. When the directory processes this request, it gives the exclusive permission, and blocks this line until the flush is done (stalls other GETS/GETX/GETF requests). If the cache line is already in a modified state (MM/M), the cache issues a BLOCK request to the directory (instead of issuing GETF as the cache already has the line exclusively), which blocks the line until the flush is done. Diffs ----- src/cpu/testers/rubytest/Check.hh baf4b5f6782e src/cpu/testers/rubytest/Check.cc baf4b5f6782e src/mem/packet.hh baf4b5f6782e src/mem/packet.cc baf4b5f6782e src/mem/physical.cc baf4b5f6782e src/mem/protocol/MOESI_hammer-cache.sm baf4b5f6782e src/mem/protocol/MOESI_hammer-dir.sm baf4b5f6782e src/mem/protocol/MOESI_hammer-msg.sm baf4b5f6782e src/mem/protocol/RubySlicc_Exports.sm baf4b5f6782e src/mem/protocol/RubySlicc_Types.sm baf4b5f6782e src/mem/ruby/slicc_interface/RubyRequest.hh baf4b5f6782e src/mem/ruby/slicc_interface/RubyRequest.cc baf4b5f6782e src/mem/ruby/system/DMASequencer.cc baf4b5f6782e src/mem/ruby/system/RubyPort.cc baf4b5f6782e src/mem/ruby/system/Sequencer.hh baf4b5f6782e src/mem/ruby/system/Sequencer.cc baf4b5f6782e Diff: http://reviews.m5sim.org/r/552/diff Testing ------- To test this implementation, I have changed the ruby tester (Check.cc). It randomly creates flushes (instead of checks (loads)). In this version, a flush request returns data, so it can be used like loads after issuing some stores (actions). Currently, this implementation passes more than 20000 ruby tests (including more than 1000 flushes), however there are still bugs, which cause deadlocks. Thanks, Somayeh _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
