changeset 9f704aa10eb4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9f704aa10eb4
description:
O3: Fix unaligned stores when cache blocked
Without this change the a store can be issued to the cache multiple
times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it
will
send a single request using the recently freed mshr and not completing
the
multipart store. This will continue forever.
diffstat:
src/cpu/o3/lsq_unit_impl.hh | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diffs (14 lines):
diff -r 2af262e73961 -r 9f704aa10eb4 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Thu Mar 17 00:43:54 2011 -0400
+++ b/src/cpu/o3/lsq_unit_impl.hh Thu Mar 17 19:20:19 2011 -0500
@@ -1103,7 +1103,9 @@
dynamic_cast<LSQSenderState *>(retryPkt->senderState);
// Don't finish the store unless this is the last packet.
- if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) {
+ if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
+ state->pendingPacket == retryPkt) {
+ state->pktToSend = false;
storePostSend(retryPkt);
}
retryPkt = NULL;
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