changeset f08692f2932e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f08692f2932e
description:
O3: Send instruction back to fetch on squash to seed predecoder
correctly.
diffstat:
src/arch/alpha/predecoder.hh | 6 ++++++
src/arch/arm/predecoder.hh | 6 ++++++
src/arch/mips/predecoder.hh | 6 ++++++
src/arch/power/predecoder.hh | 6 ++++++
src/arch/sparc/predecoder.hh | 7 +++++++
src/arch/x86/predecoder.hh | 6 ++++++
src/cpu/o3/cpu.cc | 5 +++--
src/cpu/o3/fetch.hh | 4 ++--
src/cpu/o3/fetch_impl.hh | 5 ++++-
src/kern/linux/events.cc | 12 ++++++++++++
10 files changed, 58 insertions(+), 5 deletions(-)
diffs (171 lines):
diff -r 48371b9fb929 -r f08692f2932e src/arch/alpha/predecoder.hh
--- a/src/arch/alpha/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/alpha/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
@@ -76,6 +76,12 @@
emiIsReady = false;
}
+ void
+ reset(const ExtMachInst &old_emi)
+ {
+ reset();
+ }
+
// Use this to give data to the predecoder. This should be used
// when there is control flow.
void
diff -r 48371b9fb929 -r f08692f2932e src/arch/arm/predecoder.hh
--- a/src/arch/arm/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
@@ -83,6 +83,12 @@
predAddrValid = false;
}
+ void reset(const ExtMachInst &old_emi)
+ {
+ reset();
+ itstate = old_emi.newItstate;
+ }
+
Predecoder(ThreadContext * _tc) :
tc(_tc), data(0)
{
diff -r 48371b9fb929 -r f08692f2932e src/arch/mips/predecoder.hh
--- a/src/arch/mips/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/mips/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
@@ -75,6 +75,12 @@
emiIsReady = false;
}
+ void
+ reset(const ExtMachInst &old_emi)
+ {
+ reset();
+ }
+
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void
diff -r 48371b9fb929 -r f08692f2932e src/arch/power/predecoder.hh
--- a/src/arch/power/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/power/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
@@ -82,6 +82,12 @@
emiIsReady = false;
}
+ void
+ reset(const ExtMachInst &old_emi)
+ {
+ reset();
+ }
+
// Use this to give data to the predecoder. This should be used
// when there is control flow.
void
diff -r 48371b9fb929 -r f08692f2932e src/arch/sparc/predecoder.hh
--- a/src/arch/sparc/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/sparc/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
@@ -68,12 +68,19 @@
}
void process() {}
+
void
reset()
{
emiIsReady = false;
}
+ void
+ reset(const ExtMachInst &old_emi)
+ {
+ reset();
+ }
+
// Use this to give data to the predecoder. This should be used
// when there is control flow.
void
diff -r 48371b9fb929 -r f08692f2932e src/arch/x86/predecoder.hh
--- a/src/arch/x86/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/x86/predecoder.hh Thu Mar 17 19:20:19 2011 -0500
@@ -174,6 +174,12 @@
state = ResetState;
}
+ void
+ reset(const ExtMachInst &old_emi)
+ {
+ reset();
+ }
+
ThreadContext * getTC()
{
return tc;
diff -r 48371b9fb929 -r f08692f2932e src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/cpu.cc Thu Mar 17 19:20:19 2011 -0500
@@ -808,8 +808,9 @@
}
// Squash Throughout Pipeline
- InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
- fetch.squash(0, squash_seq_num, tid);
+ DynInstPtr inst = commit.rob->readHeadInst(tid);
+ InstSeqNum squash_seq_num = inst->seqNum;
+ fetch.squash(0, squash_seq_num, inst, tid);
decode.squash(tid);
rename.squash(squash_seq_num, tid);
iew.squash(tid);
diff -r 48371b9fb929 -r f08692f2932e src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/fetch.hh Thu Mar 17 19:20:19 2011 -0500
@@ -312,8 +312,8 @@
* remove any instructions that are not in the ROB. The source of this
* squash should be the commit stage.
*/
- void squash(const TheISA::PCState &newPC,
- const InstSeqNum &seq_num, ThreadID tid);
+ void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
+ DynInstPtr &squashInst, ThreadID tid);
/** Ticks the fetch stage, processing all inputs signals and fetching
* as many instructions as possible.
diff -r 48371b9fb929 -r f08692f2932e src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/fetch_impl.hh Thu Mar 17 19:20:19 2011 -0500
@@ -815,11 +815,14 @@
template <class Impl>
void
DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
- const InstSeqNum &seq_num, ThreadID tid)
+ const InstSeqNum &seq_num, DynInstPtr &squashInst,
+ ThreadID tid)
{
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
doSquash(newPC, tid);
+ if (squashInst)
+ predecoder.reset(squashInst->staticInst->machInst);
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid);
diff -r 48371b9fb929 -r f08692f2932e src/kern/linux/events.cc
--- a/src/kern/linux/events.cc Thu Mar 17 19:20:19 2011 -0500
+++ b/src/kern/linux/events.cc Thu Mar 17 19:20:19 2011 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
