changeset ce34f14c1f43 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ce34f14c1f43
description:
Stats: Update the statistics for rfe patch.
diffstat:
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini | 2 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 8 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 32 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini | 4 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simout | 10 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 150 +++++++-------
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini | 2 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout | 8 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 46 ++--
tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 8 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 8 +-
11 files changed, 139 insertions(+), 139 deletions(-)
diffs (truncated from 643 to 300 lines):
diff -r 7449084b1612 -r ce34f14c1f43
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Mar 17
19:20:19 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Mar 17
19:20:20 2011 -0500
@@ -493,7 +493,7 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 7449084b1612 -r ce34f14c1f43
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Thu Mar 17 19:20:19
2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Thu Mar 17 19:20:20
2011 -0500
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 14:34:24
+M5 compiled Feb 22 2011 10:22:27
+M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip
+M5 started Feb 22 2011 10:22:49
M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff -r 7449084b1612 -r ce34f14c1f43
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Thu Mar 17
19:20:19 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Thu Mar 17
19:20:20 2011 -0500
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 84615 #
Simulator instruction rate (inst/s)
-host_mem_usage 256696 #
Number of bytes of host memory used
-host_seconds 7097.77 #
Real time elapsed on the host
-host_tick_rate 30571310 #
Simulator tick rate (ticks/s)
+host_inst_rate 123576 #
Simulator instruction rate (inst/s)
+host_mem_usage 255024 #
Number of bytes of host memory used
+host_seconds 4860.01 #
Real time elapsed on the host
+host_tick_rate 44647688 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 600581343 #
Number of instructions simulated
sim_seconds 0.216988 #
Number of seconds simulated
@@ -119,9 +119,9 @@
system.cpu.dcache.total_refs 208054728 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 90723000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 394050 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 84141897 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 763381678 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 172755507 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:BlockedCycles 84141899 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 763381679 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 172755505 #
Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 145178933 #
Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 17467706 #
Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 13550939 #
Number of cycles decode is unblocking
@@ -165,8 +165,8 @@
system.cpu.fetch.rateDist::1 26620223 6.15% 68.81% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 18536414 4.28% 73.09% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 23464508 5.42% 78.50% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 11465886 2.65% 81.15% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 12676535 2.93% 84.08% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 11465885 2.65% 81.15% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 12676536 2.93% 84.08% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5122176 1.18% 85.26% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7816549 1.80% 87.07% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 56018228 12.93% 100.00% #
Number of instructions fetched each cycle (Total)
@@ -492,22 +492,22 @@
system.cpu.rename.RENAME:BlockCycles 12394449 #
Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 469246940 #
Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 63310870 #
Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 190431449 #
Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 190431447 #
Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 3181742 #
Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1 #
Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 2146129409 #
Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenameLookups 2146129408 #
Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 749361548 #
Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 579635255 #
Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RenamedOperands 579635256 #
Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 140764920 #
Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 17467706 #
Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 71980154 #
Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 110388312 #
Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:UndoneMaps 110388313 #
Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 96
# Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 2146129313
# Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 56304
# count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:int_rename_lookups 2146129312
# Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 56306
# count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3959 #
count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 128598458 #
count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 3953
# count of temporary serializing insts renamed
+system.cpu.rename.RENAME:tempSerializingInsts 3954
# count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1130320351 #
The number of ROB reads
system.cpu.rob.rob_writes 1461345715 #
The number of ROB writes
system.cpu.timesIdled 36569 #
Number of times that the entire CPU went into an idle state and unscheduled
itself
diff -r 7449084b1612 -r ce34f14c1f43
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini Thu Mar 17
19:20:19 2011 -0500
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini Thu Mar 17
19:20:20 2011 -0500
@@ -493,9 +493,9 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
diff -r 7449084b1612 -r ce34f14c1f43
tests/long/20.parser/ref/arm/linux/o3-timing/simout
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout Thu Mar 17
19:20:19 2011 -0500
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout Thu Mar 17
19:20:20 2011 -0500
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 15:43:32
+M5 compiled Feb 22 2011 10:22:27
+M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip
+M5 started Feb 22 2011 10:22:49
M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d
build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d
build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -72,4 +72,4 @@
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 365986074500 because target called exit()
+Exiting @ tick 365986112500 because target called exit()
diff -r 7449084b1612 -r ce34f14c1f43
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt Thu Mar 17
19:20:19 2011 -0500
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt Thu Mar 17
19:20:20 2011 -0500
@@ -1,29 +1,29 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 77433 #
Simulator instruction rate (inst/s)
-host_mem_usage 260740 #
Number of bytes of host memory used
-host_seconds 7232.86 #
Real time elapsed on the host
-host_tick_rate 50600448 #
Simulator tick rate (ticks/s)
+host_inst_rate 97202 #
Simulator instruction rate (inst/s)
+host_mem_usage 259080 #
Number of bytes of host memory used
+host_seconds 5761.84 #
Real time elapsed on the host
+host_tick_rate 63518944 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 560059971 #
Number of instructions simulated
sim_seconds 0.365986 #
Number of seconds simulated
-sim_ticks 365986074500 #
Number of ticks simulated
+sim_ticks 365986112500 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 140387936 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 174401300 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 140387928 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 174400171 #
Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 #
Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 15511612 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 191766015 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 191766015 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 191749151 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 191749151 #
Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 #
Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 110089780 #
Number of branches committed
system.cpu.commit.COM:bw_lim_events 3558142 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 662070266
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 662070279
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.847952
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.257926
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 343782937 51.93%
51.93% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 343782950 51.93%
51.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 194895590 29.44%
81.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 65587700 9.91%
91.27% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 25120372 3.79%
95.06% # Number of insts commited each cycle
@@ -35,7 +35,7 @@
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 662070266
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 662070279
# Number of insts commited each cycle
system.cpu.commit.COM:count 561403855 #
Number of instructions committed
system.cpu.commit.COM:fp_insts 16 #
Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 #
Number of function calls committed.
@@ -97,7 +97,7 @@
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.992547 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4065.472807 #
Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 4065.472811 #
Average occupied blocks per context
system.cpu.dcache.overall_accesses 205633216 #
number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12753.485870
# average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8794.286111
# average overall mshr miss latency
@@ -115,13 +115,13 @@
system.cpu.dcache.replacements 1169307 #
number of replacements
system.cpu.dcache.sampled_refs 1173403 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4065.472807 #
Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4065.472811 #
Cycle average of tags in use
system.cpu.dcache.total_refs 203333005 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 6053772000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1049504 #
number of writebacks
system.cpu.decode.DECODE:BlockedCycles 23915687 #
Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 1082602718 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 296214320 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:IdleCycles 296214333 #
Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 338871926 #
Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 65446321 #
Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 3068332 #
Number of cycles decode is unblocking
@@ -146,23 +146,23 @@
system.cpu.dtb.write_accesses 0 #
DTB write accesses
system.cpu.dtb.write_hits 0 #
DTB write hits
system.cpu.dtb.write_misses 0 #
DTB write misses
-system.cpu.fetch.Branches 191766015 #
Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 122748340 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 351971872 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 3710699 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Branches 191749151 #
Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 122693966 #
Number of cache lines fetched
+system.cpu.fetch.Cycles 352026246 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 3656325 #
Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 938893733 #
Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 4527385 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
system.cpu.fetch.SquashCycles 26711690 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.261985 #
Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 122748340 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 140387936 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.282691 #
Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 727516586 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.537241 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.455426 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.261962 #
Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 122693966 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 140387928 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.282690 #
Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 727516599 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.537316 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.455394 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 376259318 51.72% 51.72% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 167730540 23.06% 74.77% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 376204957 51.71% 51.71% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 167784914 23.06% 74.77% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 28515235 3.92% 78.69% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 34553707 4.75% 83.44% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 26720758 3.67% 87.12% #
Number of instructions fetched each cycle (Total)
@@ -173,53 +173,53 @@
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 727516586 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 727516599 #
Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 #
number of floating regfile reads
-system.cpu.icache.ReadReq_accesses 122748340 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13369.913613
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 9679.346455
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 122731555 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 224414000 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 122693966 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 13369.943402
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 9679.377996
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 122677181 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 224414500 #
number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000137 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 16785 #
number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 933 #
number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 153437000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 153437500
# number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000129 #
mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 15852 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 7742.827266 #
Average number of references to valid blocks.
+system.cpu.icache.avg_refs 7739.396947 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 122748340 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13369.913613 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 9679.346455
# average overall mshr miss latency
-system.cpu.icache.demand_hits 122731555 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 224414000 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 122693966 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 13369.943402 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 9679.377996
# average overall mshr miss latency
+system.cpu.icache.demand_hits 122677181 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 224414500 #
number of demand (read+write) miss cycles
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