changeset d062791aad69 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d062791aad69
description:
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
diffstat:
tests/SConscript
| 3 +-
tests/configs/realview-o3.py
| 99 +
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
| 3 +
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
| 8 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
| 782 ++++----
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
| 210 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 950 ++++++++++
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
| 43 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
| 16 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 750 +++++++
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
| 1 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
| 0
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
| 7 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
| 787 ++++----
tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
| 4 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
| 7 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
| 182 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
| 3 +
tests/long/20.parser/ref/arm/linux/o3-timing/simout
| 8 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
| 782 ++++----
tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
| 4 +-
tests/long/20.parser/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
| 7 +-
tests/long/20.parser/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
| 250 +-
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/30.eon/ref/arm/linux/o3-timing/simout
| 12 +-
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
| 773 ++++----
tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/30.eon/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/30.eon/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
| 164 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
| 3 +
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
| 8 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 777 ++++----
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
| 194 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 803 ++++----
tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
| 236 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 792 ++++----
tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
| 202 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/simout
| 12 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
| 778 ++++----
tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
| 12 +-
tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/simout
| 12 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
| 160 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
| 3 +
tests/quick/00.hello/ref/arm/linux/o3-timing/simout
| 8 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
| 746 +++---
tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
| 34 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/simout
| 10 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
| 186 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 358 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
| 2 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 8 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 24 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
| 2 +-
98 files changed, 6926 insertions(+), 4866 deletions(-)
diffs (truncated from 15389 to 300 lines):
diff -r 12bd3ad81f9d -r d062791aad69 tests/SConscript
--- a/tests/SConscript Thu Mar 17 19:20:20 2011 -0500
+++ b/tests/SConscript Thu Mar 17 19:20:22 2011 -0500
@@ -276,7 +276,8 @@
't1000-simple-timing']
if env['TARGET_ISA'] == 'arm':
configs += ['realview-simple-atomic',
- 'realview-simple-timing']
+ 'realview-simple-timing',
+ 'realview-o3']
if env['TARGET_ISA'] == 'x86':
configs += ['pc-simple-atomic',
'pc-simple-timing']
diff -r 12bd3ad81f9d -r d062791aad69 tests/configs/realview-o3.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/realview-o3.py Thu Mar 17 19:20:22 2011 -0500
@@ -0,0 +1,99 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='128MB')
+ forward_snoops = False
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff -r 12bd3ad81f9d -r d062791aad69
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Mar 17
19:20:20 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Mar 17
19:20:22 2011 -0500
@@ -115,6 +115,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@@ -413,6 +414,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@@ -448,6 +450,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
diff -r 12bd3ad81f9d -r d062791aad69
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Thu Mar 17 19:20:20
2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Thu Mar 17 19:20:22
2011 -0500
@@ -5,9 +5,9 @@
All Rights Reserved
-M5 compiled Feb 22 2011 10:22:27
-M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip
-M5 started Feb 22 2011 10:22:49
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:13
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.fast -d
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -43,4 +43,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 216988269500 because target called exit()
+Exiting @ tick 212151683000 because target called exit()
diff -r 12bd3ad81f9d -r d062791aad69
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Thu Mar 17
19:20:20 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Thu Mar 17
19:20:22 2011 -0500
@@ -1,130 +1,142 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 123576 #
Simulator instruction rate (inst/s)
-host_mem_usage 255024 #
Number of bytes of host memory used
-host_seconds 4860.01 #
Real time elapsed on the host
-host_tick_rate 44647688 #
Simulator tick rate (ticks/s)
+host_inst_rate 130169 #
Simulator instruction rate (inst/s)
+host_mem_usage 255152 #
Number of bytes of host memory used
+host_seconds 4627.51 #
Real time elapsed on the host
+host_tick_rate 45845717 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 600581343 #
Number of instructions simulated
-sim_seconds 0.216988 #
Number of seconds simulated
-sim_ticks 216988269500 #
Number of ticks simulated
+sim_insts 602359950 #
Number of instructions simulated
+sim_seconds 0.212152 #
Number of seconds simulated
+sim_ticks 212151683000 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 80605280 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 86769998 #
Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 0 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 3926724 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 92457743 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 92457743 #
Number of BP lookups
-system.cpu.BPredUnit.usedRAS 0 #
Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches 70067581 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 7237688 #
number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits 77353146 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 83702663 #
Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 1593 #
Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 3826409 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 84369915 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 91120892 #
Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1482138 #
Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 70826872 #
Number of branches committed
+system.cpu.commit.COM:bw_lim_events 7259535 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 415627277
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.445000
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.803105
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 408127750
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.475910
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.811076
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 151327612 36.41%
36.41% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 131463127 31.63%
68.04% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 59591085 14.34%
82.38% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 19300079 4.64%
87.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 16801337 4.04%
91.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 14774918 3.55%
94.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 12865599 3.10%
97.71% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 2265832 0.55%
98.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 7237688 1.74%
100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 143768271 35.23%
35.23% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 130628056 32.01%
67.23% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 60243177 14.76%
81.99% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 18962619 4.65%
86.64% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 17622510 4.32%
90.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 14296756 3.50%
94.46% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 13120148 3.21%
97.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 2226678 0.55%
98.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 7259535 1.78%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 415627277
# Number of insts commited each cycle
-system.cpu.commit.COM:count 600581394 #
Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total 408127750
# Number of insts commited each cycle
+system.cpu.commit.COM:count 602360001 #
Number of instructions committed
system.cpu.commit.COM:fp_insts 16 #
Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls 0 #
Number of function calls committed.
-system.cpu.commit.COM:int_insts 531746837 #
Number of committed integer instructions.
-system.cpu.commit.COM:loads 148953025 #
Number of loads committed
-system.cpu.commit.COM:membars 0 #
Number of memory barriers committed
-system.cpu.commit.COM:refs 219174038 #
Number of memory references committed
+system.cpu.commit.COM:function_calls 997573 #
Number of function calls committed.
+system.cpu.commit.COM:int_insts 533522759 #
Number of committed integer instructions.
+system.cpu.commit.COM:loads 148952624 #
Number of loads committed
+system.cpu.commit.COM:membars 1328 #
Number of memory barriers committed
+system.cpu.commit.COM:refs 219173667 #
Number of memory references committed
system.cpu.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4754311 #
The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 600581394 #
The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 3642 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 121349980 #
The number of squashed insts skipped by commit
-system.cpu.committedInsts 600581343 #
Number of Instructions Simulated
-system.cpu.committedInsts_total 600581343 #
Number of Instructions Simulated
-system.cpu.cpi 0.722594 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.722594 #
CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 140357692 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13126.895414
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.393105
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 140121332 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3102673000 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001684 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 236360 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 40725 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1525443000
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001394 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 195635 #
number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 69418858 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 17787.364223
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.276216
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 67933393 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 26422506996 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.021399 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1485465 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1237601 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2567939504
# number of WriteReq MSHR miss cycles
+system.cpu.commit.branchMispredicts 3887306 #
The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 602360001 #
The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 6327 #
The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 105586113 #
The number of squashed insts skipped by commit
+system.cpu.committedInsts 602359950 #
Number of Instructions Simulated
+system.cpu.committedInsts_total 602359950 #
Number of Instructions Simulated
+system.cpu.cpi 0.704402 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.704402 #
CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 1392 #
number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 10807.692308
# average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits 1379 #
number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 140500
# number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.009339 #
miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 13 #
number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits 13 #
number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses 139573989 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13187.861272
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7875.361074
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 139338017 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3111966000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001691 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 235972 #
number of ReadReq misses
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