> On 2011-03-17 18:09:40, Korey Sewell wrote: > > src/arch/isa_parser.py, line 184 > > <http://reviews.m5sim.org/r/587/diff/1/?file=11010#file11010line184> > > > > Hi Gabe, not to be nitpicky but what are you trying to accomplish with > > this change? > > > > I have no objection to it, I'm just trying to understand how this > > applies to a particular line of code in defining an instruction. > > > > Is there a short example you can provide that demonstrates what kind of > > ISA-description you will be able to use with this?
This fixes a bug in the earlier support I added that integrates the new PCState stuff into the ISA parser. If you use op_decl then everything would be fine, but if you use op_src_decl or op_dest_decl then the declaration I'm adding in here will be missing and it won't compile. I was adding some code as part of some other work I'm doing and ran into this, and the fix can be applied independently of that other code. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/587/#review970 ----------------------------------------------------------- On 2011-03-17 14:51:31, Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/587/ > ----------------------------------------------------------- > > (Updated 2011-03-17 14:51:31) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ISA parser: Set up op_src_decl and op_dest_decl for pc operands. > > > Diffs > ----- > > src/arch/isa_parser.py 5138d1e453f1 > > Diff: http://reviews.m5sim.org/r/587/diff > > > Testing > ------- > > > Thanks, > > Gabe > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
