changeset d2cf4b19e8ad in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d2cf4b19e8ad
description:
MOESI_CMP_directory: significant dma bug fixes
diffstat:
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 67 ++++++++-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 171 ++++++++++++++++++++---
src/mem/protocol/MOESI_CMP_directory-dir.sm | 27 +++-
src/mem/protocol/MOESI_CMP_directory-dma.sm | 4 +
src/mem/protocol/MOESI_CMP_directory-msg.sm | 1 -
5 files changed, 233 insertions(+), 37 deletions(-)
diffs (truncated from 637 to 300 lines):
diff -r 9a6a02a235f1 -r d2cf4b19e8ad
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Fri Mar 18 14:12:04
2011 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Mar 19 14:17:48
2011 -0700
@@ -663,10 +663,27 @@
}
+ action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") {
+ peek(requestNetwork_in, RequestMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceResponseType:DMA_ACK;
+ out_msg.Sender := machineID;
+ out_msg.SenderMachine := MachineType:L1Cache;
+ out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits));
+ out_msg.Dirty := false;
+ out_msg.Acks := 1;
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ }
+ }
+ }
+
action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
peek(requestNetwork_in, RequestMsg) {
assert(is_valid(tbe));
- if (in_msg.RequestorMachine == MachineType:L1Cache) {
+ if (in_msg.RequestorMachine == MachineType:L1Cache ||
+ in_msg.RequestorMachine == MachineType:DMA) {
enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -895,11 +912,17 @@
l_popForwardQueue;
}
- transition(S, {Fwd_GETS, Fwd_DMA}) {
+ transition(S, Fwd_GETS) {
e_sendData;
l_popForwardQueue;
}
+ transition(S, Fwd_DMA) {
+ e_sendData;
+ ub_dmaUnblockL2Cache;
+ l_popForwardQueue;
+ }
+
// Transitions from Owned
transition({O, OM}, {Load, Ifetch}) {
h_load_hit;
@@ -924,11 +947,17 @@
l_popForwardQueue;
}
- transition(O, {Fwd_GETS, Fwd_DMA}) {
+ transition(O, Fwd_GETS) {
e_sendData;
l_popForwardQueue;
}
+ transition(O, Fwd_DMA) {
+ e_sendData;
+ ub_dmaUnblockL2Cache;
+ l_popForwardQueue;
+ }
+
// Transitions from MM
transition({MM, MM_W}, {Load, Ifetch}) {
h_load_hit;
@@ -957,8 +986,8 @@
}
transition(MM, Fwd_DMA, MM) {
- //ee_sendDataExclusive;
e_sendData;
+ ub_dmaUnblockL2Cache;
l_popForwardQueue;
}
@@ -995,8 +1024,9 @@
l_popForwardQueue;
}
- transition(M, Fwd_DMA, M) {
+ transition(M, Fwd_DMA) {
e_sendData;
+ ub_dmaUnblockL2Cache;
l_popForwardQueue;
}
@@ -1039,11 +1069,17 @@
n_popResponseQueue;
}
- transition(SM, {Fwd_DMA, Fwd_GETS}) {
+ transition(SM, Fwd_GETS) {
e_sendData;
l_popForwardQueue;
}
+ transition(SM, Fwd_DMA) {
+ e_sendData;
+ ub_dmaUnblockL2Cache;
+ l_popForwardQueue;
+ }
+
// Transitions from OM
transition(OM, Own_GETX) {
mm_decrementNumberOfMessages;
@@ -1058,11 +1094,17 @@
l_popForwardQueue;
}
- transition(OM, {Fwd_DMA, Fwd_GETS}, OM) {
+ transition(OM, Fwd_GETS) {
e_sendData;
l_popForwardQueue;
}
+ transition(OM, Fwd_DMA) {
+ e_sendData;
+ ub_dmaUnblockL2Cache;
+ l_popForwardQueue;
+ }
+
//transition({OM, OMF}, Ack) {
transition(OM, Ack) {
m_decrementNumberOfMessages;
@@ -1119,8 +1161,9 @@
l_popForwardQueue;
}
- transition(MI, Fwd_DMA, MI) {
+ transition(MI, Fwd_DMA) {
q_sendDataFromTBEToCache;
+ ub_dmaUnblockL2Cache;
l_popForwardQueue;
}
@@ -1129,11 +1172,17 @@
l_popForwardQueue;
}
- transition({SI, OI}, {Fwd_DMA, Fwd_GETS}) {
+ transition({SI, OI}, Fwd_GETS) {
q_sendDataFromTBEToCache;
l_popForwardQueue;
}
+ transition({SI, OI}, Fwd_DMA) {
+ q_sendDataFromTBEToCache;
+ ub_dmaUnblockL2Cache;
+ l_popForwardQueue;
+ }
+
transition(OI, Fwd_GETX, II) {
q_sendExclusiveDataFromTBEToCache;
l_popForwardQueue;
diff -r 9a6a02a235f1 -r d2cf4b19e8ad
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Fri Mar 18 14:12:04
2011 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Sat Mar 19 14:17:48
2011 -0700
@@ -125,6 +125,13 @@
MII, AccessPermission:Busy, desc="Blocked, doing writeback, was M, got
Fwd_GETX";
OLSI, AccessPermission:Busy, desc="Blocked, doing writeback, was OLS";
ILSI, AccessPermission:Busy, desc="Blocked, doing writeback, was OLS got
Fwd_GETX";
+
+ // DMA blocking states
+ ILOSD, AccessPermission:Busy, desc="Blocked, waiting for DMA ack";
+ ILOSXD, AccessPermission:Busy, desc="Blocked, waiting for DMA ack";
+ ILOD, AccessPermission:Busy, desc="Blocked, waiting for DMA ack";
+ ILXD, AccessPermission:Busy, desc="Blocked, waiting for DMA ack";
+ ILOXD, AccessPermission:Busy, desc="Blocked, waiting for DMA ack";
}
// EVENTS
@@ -158,7 +165,7 @@
Unblock, desc="Local L1 is telling L2 dir to unblock";
Exclusive_Unblock, desc="Local L1 is telling L2 dir to unblock";
-
+ DmaAck, desc="DMA ack from local L1";
// events initiated by this L2
L2_Replacement, desc="L2 Replacement", format="!r";
@@ -636,6 +643,9 @@
trigger(Event:L1_WBCLEANDATA, in_msg.Address,
cache_entry, TBEs[in_msg.Address]);
}
+ } else if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
+ trigger(Event:DmaAck, in_msg.Address,
+ getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
} else {
error("Unexpected message");
}
@@ -769,6 +779,26 @@
}
}
+ action(cd_sendDataFromTBEToFwdDma, "cd", desc="Send data from TBE to
external GETX") {
+ assert(is_valid(tbe));
+ peek(requestNetwork_in, RequestMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.DataBlk := tbe.DataBlk;
+ // out_msg.Dirty := tbe.Dirty;
+ // shared data should be clean
+ out_msg.Dirty := false;
+ out_msg.Acks := tbe.Fwd_GETX_ExtAcks;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+ DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+ address, tbe.DataBlk);
+ }
+
action(c_sendDataFromTBEToFwdGETS, "ccc", desc="Send data from TBE to
external GETX") {
assert(is_valid(tbe));
enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
@@ -1114,6 +1144,7 @@
assert(is_valid(tbe));
tbe.DataBlk := in_msg.DataBlk;
tbe.Dirty := in_msg.Dirty;
+ APPEND_TRANSITION_COMMENT(in_msg.Sender);
}
}
@@ -1148,6 +1179,21 @@
}
}
+ action(jd_forwardDmaRequestToLocalOwner, "jd", desc="Forward dma request to
local owner") {
+ peek(requestNetwork_in, RequestMsg) {
+ enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency )
{
+ out_msg.Address := in_msg.Address;
+ out_msg.Type := in_msg.Type;
+ out_msg.Requestor := in_msg.Requestor;
+ out_msg.RequestorMachine := in_msg.RequestorMachine;
+ out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Address));
+ out_msg.Type := in_msg.Type;
+ out_msg.MessageSize := MessageSizeType:Forwarded_Control;
+ out_msg.Acks := 0 - 1;
+ }
+ }
+ }
+
action(k_forwardLocalGETSToLocalSharer, "k", desc="Forward local request to
local sharer/owner") {
peek(L1requestNetwork_in, RequestMsg) {
@@ -1436,33 +1482,48 @@
responseNetwork_in.recycle();
}
+ action(da_sendDmaAckUnblock, "da", desc="Send dma ack to global directory") {
+ enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceResponseType:DMA_ACK;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.Sender := machineID;
+ out_msg.SenderMachine := MachineType:L2Cache;
+ out_msg.MessageSize := MessageSizeType:Unblock_Control;
+ }
+ }
+
//*****************************************************
// TRANSITIONS
//*****************************************************
- transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF, MM,
SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS}, {L1_PUTO, L1_PUTS,
L1_PUTS_only, L1_PUTX}) {
+ transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF, MM,
SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD,
ILOD, ILXD, ILOXD}, {L1_PUTO, L1_PUTS, L1_PUTS_only, L1_PUTX}) {
zz_recycleL1RequestQueue;
}
- transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF, MM,
SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS}, {L1_GETX,
L1_GETS}) {
+ transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF, MM,
SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD,
ILOD, ILXD, ILOXD}, {L1_GETX, L1_GETS}) {
zz_recycleL1RequestQueue;
}
- transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX,OLSXS, IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII, OLSI,
ILSI, SLSS, OLSS, OLSF, IGMIOFS}, L2_Replacement) {
+ transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX,OLSXS, IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII, OLSI,
ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD},
L2_Replacement) {
zz_recycleResponseQueue;
}
- transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX,OLSXS, IGS, IGM, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS},
{Fwd_GETX, Fwd_GETS, Fwd_DMA}) {
+ transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX,OLSXS, IGS, IGM, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD,
ILOSXD, ILOD, ILXD, ILOXD}, {Fwd_GETX, Fwd_GETS, Fwd_DMA}) {
zz_recycleRequestQueue;
}
- transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX,OLSXS, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS}, {Inv}) {
+ transition({OGMIO, IGMIO, IGMO}, Fwd_DMA) {
zz_recycleRequestQueue;
}
- transition({IGM, IGS}, {Own_GETX}) {
+ transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,
IFLOXX, IFLOSX,OLSXS, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD,
ILOD, ILXD, ILOXD}, {Inv}) {
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