changeset b043c0efa024 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b043c0efa024
description:
Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.
diffstat:
src/cpu/testers/rubytest/Check.cc | 2 +-
src/cpu/testers/rubytest/Check.hh | 4 ++--
src/mem/protocol/MESI_CMP_directory-msg.sm | 2 +-
src/mem/protocol/MOESI_CMP_directory-msg.sm | 2 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 2 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 8 ++++----
src/mem/protocol/MOESI_CMP_token-msg.sm | 4 ++--
src/mem/protocol/RubySlicc_Exports.sm | 13 +++++++------
src/mem/protocol/RubySlicc_Types.sm | 2 +-
src/mem/ruby/profiler/AccessTraceForAddress.cc | 4 ++--
src/mem/ruby/profiler/AccessTraceForAddress.hh | 4 ++--
src/mem/ruby/profiler/AddressProfiler.cc | 6 +++---
src/mem/ruby/profiler/AddressProfiler.hh | 2 +-
src/mem/ruby/profiler/CacheProfiler.cc | 12 ++++++------
src/mem/ruby/profiler/CacheProfiler.hh | 10 +++++-----
src/mem/ruby/profiler/Profiler.hh | 2 +-
src/mem/ruby/slicc_interface/RubyRequest.hh | 8 +-------
src/mem/ruby/system/CacheMemory.cc | 2 +-
src/mem/ruby/system/CacheMemory.hh | 2 +-
src/mem/ruby/system/Sequencer.cc | 10 +++++-----
src/mem/ruby/system/Sequencer.hh | 4 ++--
21 files changed, 50 insertions(+), 55 deletions(-)
diffs (truncated from 471 to 300 lines):
diff -r 19a654839a04 -r b043c0efa024 src/cpu/testers/rubytest/Check.cc
--- a/src/cpu/testers/rubytest/Check.cc Sat Mar 19 14:17:48 2011 -0700
+++ b/src/cpu/testers/rubytest/Check.cc Sat Mar 19 18:34:37 2011 -0500
@@ -44,7 +44,7 @@
pickInitiatingNode();
changeAddress(address);
m_pc = pc;
- m_access_mode = AccessModeType(random() % AccessModeType_NUM);
+ m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM);
m_store_count = 0;
}
diff -r 19a654839a04 -r b043c0efa024 src/cpu/testers/rubytest/Check.hh
--- a/src/cpu/testers/rubytest/Check.hh Sat Mar 19 14:17:48 2011 -0700
+++ b/src/cpu/testers/rubytest/Check.hh Sat Mar 19 18:34:37 2011 -0500
@@ -33,7 +33,7 @@
#include <iostream>
#include "cpu/testers/rubytest/RubyTester.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/TesterStatus.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
@@ -73,7 +73,7 @@
NodeID m_initiatingNode;
Address m_address;
Address m_pc;
- AccessModeType m_access_mode;
+ RubyAccessMode m_access_mode;
int m_num_cpu_sequencers;
RubyTester* m_tester_ptr;
};
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/MESI_CMP_directory-msg.sm
--- a/src/mem/protocol/MESI_CMP_directory-msg.sm Sat Mar 19 14:17:48
2011 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-msg.sm Sat Mar 19 18:34:37
2011 -0500
@@ -62,7 +62,7 @@
structure(RequestMsg, desc="...", interface="NetworkMessage") {
Address Address, desc="Physical address for this request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
MachineID Requestor , desc="What component request";
NetDest Destination, desc="What components receive the request,
includes MachineType and num";
MessageSizeType MessageSize, desc="size category of the message";
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/MOESI_CMP_directory-msg.sm
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm Sat Mar 19 14:17:48
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm Sat Mar 19 18:34:37
2011 -0500
@@ -84,7 +84,7 @@
DataBlock DataBlk, desc="data for the cache line (DMA WRITE
request)";
int Acks, desc="How many acks to expect";
MessageSizeType MessageSize, desc="size category of the message";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Mar 19 14:17:48
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Mar 19 18:34:37
2011 -0500
@@ -149,7 +149,7 @@
AccessType AccessType, desc="Type of request (used for
profiling)";
Time IssueTime, desc="Time the request was issued";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Sat Mar 19 18:34:37 2011 -0500
@@ -424,7 +424,7 @@
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control;
out_msg.Prefetch := PrefetchBit:No;
- out_msg.AccessMode := AccessModeType:SupervisorMode;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
}
markPersistentEntries(address);
starving := true;
@@ -466,7 +466,7 @@
out_msg.RetryNum := 0;
out_msg.MessageSize := MessageSizeType:Broadcast_Control;
out_msg.Prefetch := PrefetchBit:No;
- out_msg.AccessMode := AccessModeType:SupervisorMode;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
}
}
}
@@ -494,7 +494,7 @@
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control;
out_msg.Prefetch := PrefetchBit:No;
- out_msg.AccessMode := AccessModeType:SupervisorMode;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
}
markPersistentEntries(address);
starving := true;
@@ -532,7 +532,7 @@
out_msg.RetryNum := 0;
out_msg.MessageSize := MessageSizeType:Broadcast_Control;
out_msg.Prefetch := PrefetchBit:No;
- out_msg.AccessMode := AccessModeType:SupervisorMode;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
}
}
}
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/MOESI_CMP_token-msg.sm
--- a/src/mem/protocol/MOESI_CMP_token-msg.sm Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-msg.sm Sat Mar 19 18:34:37 2011 -0500
@@ -78,7 +78,7 @@
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination set";
MessageSizeType MessageSize, desc="size category of the message";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
@@ -91,7 +91,7 @@
bool isLocal, desc="Is this request from a local L1";
int RetryNum, desc="retry sequence number";
MessageSizeType MessageSize, desc="size category of the message";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/protocol/RubySlicc_Exports.sm Sat Mar 19 18:34:37 2011 -0500
@@ -193,10 +193,11 @@
Write, desc="Writing to cache";
}
-// AccessModeType
-enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") {
- SupervisorMode, desc="Supervisor mode";
- UserMode, desc="User mode";
+// RubyAccessMode
+enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
+ Supervisor, desc="Supervisor mode";
+ User, desc="User mode";
+ Device, desc="Device mode";
}
enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
@@ -212,7 +213,7 @@
Address PhysicalAddress, desc="Physical address for this request";
CacheRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that
caused the miss";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
@@ -223,7 +224,7 @@
Address PhysicalAddress, desc="Physical address for this request";
SequencerRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that
caused the miss";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
DataBlock DataBlk, desc="Data";
int Len, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/protocol/RubySlicc_Types.sm Sat Mar 19 18:34:37 2011 -0500
@@ -129,7 +129,7 @@
void profileMiss(CacheMsg);
void profileGenericRequest(GenericRequestType,
- AccessModeType,
+ RubyAccessMode,
PrefetchBit);
void setMRU(Address);
diff -r 19a654839a04 -r b043c0efa024
src/mem/ruby/profiler/AccessTraceForAddress.cc
--- a/src/mem/ruby/profiler/AccessTraceForAddress.cc Sat Mar 19 14:17:48
2011 -0700
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.cc Sat Mar 19 18:34:37
2011 -0500
@@ -59,7 +59,7 @@
void
AccessTraceForAddress::update(CacheRequestType type,
- AccessModeType access_mode, NodeID cpu,
+ RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss)
{
m_touched_by.add(cpu);
@@ -74,7 +74,7 @@
// ERROR_MSG("Trying to add invalid access to trace");
}
- if (access_mode == AccessModeType_UserMode) {
+ if (access_mode == RubyAccessMode_User) {
m_user++;
}
diff -r 19a654839a04 -r b043c0efa024
src/mem/ruby/profiler/AccessTraceForAddress.hh
--- a/src/mem/ruby/profiler/AccessTraceForAddress.hh Sat Mar 19 14:17:48
2011 -0700
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh Sat Mar 19 18:34:37
2011 -0500
@@ -31,7 +31,7 @@
#include <iostream>
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
@@ -50,7 +50,7 @@
~AccessTraceForAddress();
void setAddress(const Address& addr) { m_addr = addr; }
- void update(CacheRequestType type, AccessModeType access_mode, NodeID cpu,
+ void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss);
int getTotal() const;
int getSharing() const { return m_sharing; }
diff -r 19a654839a04 -r b043c0efa024 src/mem/ruby/profiler/AddressProfiler.cc
--- a/src/mem/ruby/profiler/AddressProfiler.cc Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/ruby/profiler/AddressProfiler.cc Sat Mar 19 18:34:37 2011 -0500
@@ -257,7 +257,7 @@
m_getx_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0);
- addTraceSample(datablock, PC, CacheRequestType_ST, AccessModeType(0),
+ addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0),
requestor, indirection_miss);
}
@@ -274,14 +274,14 @@
m_gets_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0);
- addTraceSample(datablock, PC, CacheRequestType_LD, AccessModeType(0),
+ addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0),
requestor, indirection_miss);
}
void
AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
CacheRequestType type,
- AccessModeType access_mode, NodeID id,
+ RubyAccessMode access_mode, NodeID id,
bool sharing_miss)
{
if (m_all_instructions) {
diff -r 19a654839a04 -r b043c0efa024 src/mem/ruby/profiler/AddressProfiler.hh
--- a/src/mem/ruby/profiler/AddressProfiler.hh Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/ruby/profiler/AddressProfiler.hh Sat Mar 19 18:34:37 2011 -0500
@@ -55,7 +55,7 @@
void clearStats();
void addTraceSample(Address data_addr, Address pc_addr,
- CacheRequestType type, AccessModeType access_mode,
+ CacheRequestType type, RubyAccessMode access_mode,
NodeID id, bool sharing_miss);
void profileRetry(const Address& data_addr, AccessType type, int count);
void profileGetX(const Address& datablock, const Address& PC,
diff -r 19a654839a04 -r b043c0efa024 src/mem/ruby/profiler/CacheProfiler.cc
--- a/src/mem/ruby/profiler/CacheProfiler.cc Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/ruby/profiler/CacheProfiler.cc Sat Mar 19 18:34:37 2011 -0500
@@ -94,10 +94,10 @@
out << endl;
- for (int i = 0; i < AccessModeType_NUM; i++){
+ for (int i = 0; i < RubyAccessMode_NUM; i++){
if (m_accessModeTypeHistogram[i] > 0) {
out << description << "_access_mode_type_"
- << (AccessModeType) i << ": "
+ << (RubyAccessMode) i << ": "
<< m_accessModeTypeHistogram[i] << " "
<< 100.0 * m_accessModeTypeHistogram[i] / requests
<< "%" << endl;
@@ -122,14 +122,14 @@
m_prefetches = 0;
m_sw_prefetches = 0;
m_hw_prefetches = 0;
- for (int i = 0; i < AccessModeType_NUM; i++) {
+ for (int i = 0; i < RubyAccessMode_NUM; i++) {
m_accessModeTypeHistogram[i] = 0;
}
}
void
CacheProfiler::addCacheStatSample(CacheRequestType requestType,
- AccessModeType accessType,
+ RubyAccessMode accessType,
PrefetchBit pfBit)
{
m_cacheRequestType[requestType]++;
@@ -138,7 +138,7 @@
void
CacheProfiler::addGenericStatSample(GenericRequestType requestType,
- AccessModeType accessType,
+ RubyAccessMode accessType,
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