changeset d8587c913ccf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d8587c913ccf
description:
ruby: fixed cache index setting
diffstat:
configs/ruby/MESI_CMP_directory.py | 17 +++++++++++------
configs/ruby/MI_example.py | 4 +++-
configs/ruby/MOESI_CMP_directory.py | 17 +++++++++++------
configs/ruby/MOESI_CMP_token.py | 15 +++++++++------
configs/ruby/MOESI_hammer.py | 10 +++++++---
5 files changed, 41 insertions(+), 22 deletions(-)
diffs (207 lines):
diff -r bbab80b639cb -r d8587c913ccf configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py Fri Mar 25 00:46:14 2011 -0400
+++ b/configs/ruby/MESI_CMP_directory.py Fri Mar 25 10:13:50 2011 -0700
@@ -68,15 +68,19 @@
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
+ l2_bits = int(math.log(options.num_l2caches, 2))
+ block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
+ assoc = options.l1i_assoc,
+ start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
@@ -91,9 +95,7 @@
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches,
- 2))
+ l2_select_num_bits = l2_bits)
exec("system.l1_cntrl%d = l1_cntrl" % i)
@@ -103,12 +105,15 @@
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ l2_index_start = block_size_bits + l2_bits
+
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
+ assoc = options.l2_assoc,
+ start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
L2cacheMemory = l2_cache)
diff -r bbab80b639cb -r d8587c913ccf configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Fri Mar 25 00:46:14 2011 -0400
+++ b/configs/ruby/MI_example.py Fri Mar 25 10:13:50 2011 -0700
@@ -60,6 +60,7 @@
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
+ block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
@@ -68,7 +69,8 @@
# config parameters.
#
cache = Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits)
#
# Only one unified L1 cache exists. Can cache instructions and data.
diff -r bbab80b639cb -r d8587c913ccf configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py Fri Mar 25 00:46:14 2011 -0400
+++ b/configs/ruby/MOESI_CMP_directory.py Fri Mar 25 10:13:50 2011 -0700
@@ -68,15 +68,19 @@
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
+ l2_bits = int(math.log(options.num_l2caches, 2))
+ block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
+ assoc = options.l1i_assoc,
+ start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
@@ -91,9 +95,7 @@
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches,
- 2))
+ l2_select_num_bits = l2_bits)
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@@ -102,12 +104,15 @@
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ l2_index_start = block_size_bits + l2_bits
+
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
+ assoc = options.l2_assoc,
+ start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
L2cacheMemory = l2_cache)
diff -r bbab80b639cb -r d8587c913ccf configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py Fri Mar 25 00:46:14 2011 -0400
+++ b/configs/ruby/MOESI_CMP_token.py Fri Mar 25 10:13:50 2011 -0700
@@ -82,15 +82,18 @@
# controller constructors are called before the network constructor
#
l2_bits = int(math.log(options.num_l2caches, 2))
+ block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
+ assoc = options.l1i_assoc,
+ start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
@@ -123,13 +126,15 @@
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ l2_index_start = block_size_bits + l2_bits
+
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
assoc = options.l2_assoc,
- start_index_bit = l2_bits)
+ start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
L2cacheMemory = l2_cache,
@@ -158,9 +163,7 @@
size = \
dir_size),
memBuffer = mem_cntrl,
- l2_select_num_bits = \
- math.log(options.num_l2caches,
- 2))
+ l2_select_num_bits = l2_bits)
exec("system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
diff -r bbab80b639cb -r d8587c913ccf configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Fri Mar 25 00:46:14 2011 -0400
+++ b/configs/ruby/MOESI_hammer.py Fri Mar 25 10:13:50 2011 -0700
@@ -78,17 +78,21 @@
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
+ block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
+ assoc = options.l1i_assoc,
+ start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits)
l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
+ assoc = options.l2_assoc,
+ start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
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