On Sun, Mar 27, 2011 at 1:27 PM, nathan binkert <n...@binkert.org> wrote: >> Is there any reason to have a serialize function in the timing and o3 cpus? >> Creating a checkpoint from them will be broken since if you're using cache >> the dirty data won't be saved? Shouldn't we change their implementation to >> fatal()? > > Is the implementation of the CPUs correct? Arguably, it should be the > caches that cause fatal() if they're what cause the problem, no?
I agree with Nate... in fact the Ruby caches do have a warm-up facility that Brad is working on porting (or says he will), so we don't want to assume that caches can't be checkpointed. Also it's possible to have a timing CPU with no caches (even though it doesn't make a lot of sense). What I would like to see is to have the O3 unserialize function fixed so that we can avoid the silly switch_cpus thing when you want to restore directly into O3... at least my understanding is that that's why we don't do it that way. Steve _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
