changeset c7302d55d644 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c7302d55d644
description:
CacheMemory: add allocateVoid() that is == allocate() but no return
value.
This function duplicates the functionality of allocate() exactly,
except that it does not return
a return value. In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry,
use this function.
Otherwise, SLICC will complain if you do not consume the pointer
returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address),
the C++
compiler will complain of an unused variable. This is kind of a hack
to get around
those issues, but suggestions welcome.
diffstat:
src/mem/protocol/RubySlicc_Types.sm | 1 +
src/mem/ruby/system/CacheMemory.hh | 4 ++++
src/mem/ruby/system/WireBuffer.hh | 3 +--
src/mem/ruby/system/WireBuffer.py | 1 -
4 files changed, 6 insertions(+), 3 deletions(-)
diffs (56 lines):
diff -r be38f7b6ad9e -r c7302d55d644 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Thu Mar 31 17:18:00 2011 -0700
+++ b/src/mem/protocol/RubySlicc_Types.sm Thu Mar 31 18:20:12 2011 -0700
@@ -134,6 +134,7 @@
bool cacheAvail(Address);
Address cacheProbe(Address);
AbstractCacheEntry allocate(Address, AbstractCacheEntry);
+ void allocateVoid(Address, AbstractCacheEntry);
void deallocate(Address);
AbstractCacheEntry lookup(Address);
bool isTagPresent(Address);
diff -r be38f7b6ad9e -r c7302d55d644 src/mem/ruby/system/CacheMemory.hh
--- a/src/mem/ruby/system/CacheMemory.hh Thu Mar 31 17:18:00 2011 -0700
+++ b/src/mem/ruby/system/CacheMemory.hh Thu Mar 31 18:20:12 2011 -0700
@@ -83,6 +83,10 @@
// find an unused entry and sets the tag appropriate for the address
AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry*
new_entry);
+ void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
+ {
+ allocate(address, new_entry);
+ }
// Explicitly free up this address
void deallocate(const Address& address);
diff -r be38f7b6ad9e -r c7302d55d644 src/mem/ruby/system/WireBuffer.hh
--- a/src/mem/ruby/system/WireBuffer.hh Thu Mar 31 17:18:00 2011 -0700
+++ b/src/mem/ruby/system/WireBuffer.hh Thu Mar 31 18:20:12 2011 -0700
@@ -54,7 +54,7 @@
/////////////////////////////////////////////////////////////////////////////
class Consumer;
-class Message; // I added this and removed Message.hh
+class Message;
class WireBuffer : public SimObject
{
@@ -88,7 +88,6 @@
void clearStats() const;
void printStats(std::ostream& out) const;
-// int m_dummy;
uint64_t m_msg_counter;
private:
diff -r be38f7b6ad9e -r c7302d55d644 src/mem/ruby/system/WireBuffer.py
--- a/src/mem/ruby/system/WireBuffer.py Thu Mar 31 17:18:00 2011 -0700
+++ b/src/mem/ruby/system/WireBuffer.py Thu Mar 31 18:20:12 2011 -0700
@@ -28,7 +28,6 @@
from m5.params import *
from m5.SimObject import SimObject
-#from Controller import RubyController
class RubyWireBuffer(SimObject):
type = 'RubyWireBuffer'
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