changeset 7ecbffb674aa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7ecbffb674aa
description:
ARM: Cleanup implementation of ITSTATE and put important code in
PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
diffstat:
src/arch/alpha/predecoder.hh | 6 --
src/arch/arm/faults.cc | 9 +-
src/arch/arm/isa.cc | 12 ----
src/arch/arm/isa/insts/data.isa | 2 +-
src/arch/arm/isa/insts/macromem.isa | 4 +-
src/arch/arm/isa/insts/misc.isa | 10 +---
src/arch/arm/isa/operands.isa | 4 +-
src/arch/arm/isa/templates/macromem.isa | 4 -
src/arch/arm/isa/templates/mem.isa | 81 -------------------------------
src/arch/arm/isa/templates/misc.isa | 7 --
src/arch/arm/isa/templates/neon.isa | 8 ---
src/arch/arm/isa/templates/pred.isa | 10 ---
src/arch/arm/miscregs.hh | 17 +------
src/arch/arm/predecoder.cc | 52 +-------------------
src/arch/arm/predecoder.hh | 22 ++-----
src/arch/arm/types.hh | 84 +++++++++++++++++++++++---------
src/arch/mips/predecoder.hh | 6 --
src/arch/power/predecoder.hh | 6 --
src/arch/sparc/predecoder.hh | 6 --
src/arch/x86/predecoder.hh | 6 --
src/cpu/o3/fetch_impl.hh | 2 -
21 files changed, 81 insertions(+), 277 deletions(-)
diffs (truncated from 885 to 300 lines):
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/alpha/predecoder.hh
--- a/src/arch/alpha/predecoder.hh Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/alpha/predecoder.hh Mon Apr 04 11:42:28 2011 -0500
@@ -76,12 +76,6 @@
emiIsReady = false;
}
- void
- reset(const ExtMachInst &old_emi)
- {
- reset();
- }
-
// Use this to give data to the predecoder. This should be used
// when there is control flow.
void
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/arm/faults.cc Mon Apr 04 11:42:28 2011 -0500
@@ -108,7 +108,9 @@
CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
tc->readIntReg(INTREG_CONDCODES);
Addr curPc M5_VAR_USED = tc->pcState().pc();
-
+ ITSTATE it = tc->pcState().itstate();
+ saved_cpsr.it2 = it.top6;
+ saved_cpsr.it1 = it.bottom2;
cpsr.mode = nextMode();
cpsr.it1 = cpsr.it2 = 0;
@@ -159,7 +161,7 @@
{
tc->getCpuPtr()->clearInterrupts();
tc->clearArchRegs();
- ArmFault::invoke(tc);
+ ArmFault::invoke(tc, inst);
}
#else
@@ -203,7 +205,7 @@
void
AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- ArmFaultVals<T>::invoke(tc);
+ ArmFaultVals<T>::invoke(tc, inst);
FSR fsr = 0;
fsr.fsLow = bits(status, 3, 0);
fsr.fsHigh = bits(status, 4);
@@ -223,7 +225,6 @@
// start refetching from the next instruction.
PCState pc = tc->pcState();
assert(inst);
- pc.forcedItState(inst->machInst.newItstate);
inst->advancePC(pc);
tc->pcState(pc);
}
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/arm/isa.cc Mon Apr 04 11:42:28 2011 -0500
@@ -266,18 +266,6 @@
miscRegName[misc_reg], val);
} else {
switch (misc_reg) {
- case MISCREG_ITSTATE:
- {
- ITSTATE itstate = newVal;
- CPSR cpsr = miscRegs[MISCREG_CPSR];
- cpsr.it1 = itstate.bottom2;
- cpsr.it2 = itstate.top6;
- miscRegs[MISCREG_CPSR] = cpsr;
- DPRINTF(MiscRegs,
- "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
- (uint8_t)itstate, (uint32_t)cpsr);
- }
- break;
case MISCREG_CPACR:
{
CPACR newCpacr = 0;
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/arm/isa/insts/data.isa
--- a/src/arch/arm/isa/insts/data.isa Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/arm/isa/insts/data.isa Mon Apr 04 11:42:28 2011 -0500
@@ -245,7 +245,7 @@
CondCodes = CondCodesMask & newCpsr;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
- ForcedItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
+ NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
| (((CPSR)newCpsr).it1 & 0x3);
'''
buildImmDataInst(mnem + 's', code, flagType,
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/arm/isa/insts/macromem.isa
--- a/src/arch/arm/isa/insts/macromem.isa Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/arm/isa/insts/macromem.isa Mon Apr 04 11:42:28 2011 -0500
@@ -94,7 +94,7 @@
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
- ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
+ NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
| (((CPSR)Spsr).it1 & 0x3);
'''
@@ -628,7 +628,7 @@
Cpsr = ~CondCodesMask & newCpsr;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
- ForcedItState = ((((CPSR)URb).it2 << 2) & 0xFC)
+ NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
| (((CPSR)URb).it1 & 0x3);
CondCodes = CondCodesMask & newCpsr;
'''
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/arm/isa/insts/misc.isa Mon Apr 04 11:42:28 2011 -0500
@@ -83,10 +83,6 @@
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false,
sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
- NextThumb = ((CPSR)newCpsr).t;
- NextJazelle = ((CPSR)newCpsr).j;
- ForcedItState = ((((CPSR)Op1).it2 << 2) & 0xFC)
- | (((CPSR)Op1).it1 & 0x3);
CondCodes = CondCodesMask & newCpsr;
'''
msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
@@ -111,10 +107,6 @@
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false,
sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
- NextThumb = ((CPSR)newCpsr).t;
- NextJazelle = ((CPSR)newCpsr).j;
- ForcedItState = ((((CPSR)imm).it2 << 2) & 0xFC)
- | (((CPSR)imm).it1 & 0x3);
CondCodes = CondCodesMask & newCpsr;
'''
msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
@@ -538,7 +530,7 @@
exec_output += PredOpExecute.subst(sevIop)
itIop = InstObjParams("it", "ItInst", "PredOp", \
- { "code" : "Itstate = machInst.newItstate;",
+ { "code" : ";",
"predicate_test" : predicateTest },
["IsNonSpeculative", "IsSerializeAfter"])
header_output += BasicDeclare.subst(itIop)
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/arm/isa/operands.isa Mon Apr 04 11:42:28 2011 -0500
@@ -217,7 +217,6 @@
#Fixed index control regs
'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
- 'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'),
'Spsr': cntrlRegNC('MISCREG_SPSR'),
'Fpsr': cntrlRegNC('MISCREG_FPSR'),
'Fpsid': cntrlRegNC('MISCREG_FPSID'),
@@ -247,7 +246,8 @@
'Thumb': pcStateReg('thumb', srtPC),
'NextThumb': pcStateReg('nextThumb', srtMode),
'NextJazelle': pcStateReg('nextJazelle', srtMode),
- 'ForcedItState': pcStateReg('forcedItState', srtMode),
+ 'NextItState': pcStateReg('nextItstate', srtMode),
+ 'Itstate': pcStateReg('itstate', srtMode),
#Register operands depending on a field in the instruction encoding. These
#should be avoided since they may not be portable across different
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/arm/isa/templates/macromem.isa
--- a/src/arch/arm/isa/templates/macromem.isa Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/arm/isa/templates/macromem.isa Mon Apr 04 11:42:28 2011 -0500
@@ -241,10 +241,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
diff -r 6c051a8df26a -r 7ecbffb674aa src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa Mon Apr 04 11:42:28 2011 -0500
+++ b/src/arch/arm/isa/templates/mem.isa Mon Apr 04 11:42:28 2011 -0500
@@ -102,11 +102,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -135,11 +130,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -166,10 +156,6 @@
}
}
- if (fault == NoFault && machInst.itstateMask != 0) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -199,11 +185,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -238,11 +219,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -276,11 +252,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -319,11 +290,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -363,11 +329,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
}};
@@ -396,10 +357,6 @@
} else {
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
return fault;
}
@@ -430,11 +387,6 @@
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0 &&
- (!isMicroop() || isLastMicroop())) {
- xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
- }
-
return fault;
}
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