On Mon, 11 Apr 2011, Beckmann, Brad wrote:
Hi Nilay,
Yes, that is a good point. We really just need the interface to the
permission to be available from AbstractEntry. The variable itself
doesn't really need to be there. However, to make that change, you'll
need to modify how CacheMemory supports atomics.
I will try to make this change later today.
Could you elaborate on your directory controller question. I suspect
that you are right and that only one type of directory controller can
exist in a system, but why is that a problem?
Brad
Is it not possible that we have a protocol in which different directory
controllers may behave differently?
--
Nilay
-----Original Message-----
From: [email protected] [mailto:[email protected]]
On Behalf Of Nilay Vaish
Sent: Sunday, April 10, 2011 2:12 AM
To: [email protected]
Subject: [m5-dev] AccessPermission in AbstractEntry
Brad, it seems like the m_Permission variable in AbstractEntry is not being
used at all. In order to get AccessPermission for a state, the
state_To_AccessPermission function needs to be called. Then, why have that
variable? And this would mean that CacheMemory has no idea about the
access permission, unless we expose the state to Cache Memory class.
Also, as it now stands, it seems one cannot have two different types of
directory controllers in a system. Is this correct? If yes, then why this
restriction?
--
Nilay
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev