changeset 38befb82b2c9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=38befb82b2c9
description:
stats: rename stats so they can be used as python expressions
diffstat:
src/cpu/inorder/pipeline_stage.cc | 2 +-
src/cpu/inorder/resource_pool.9stage.cc | 39 +++++++++++++++++++-----------
src/cpu/inorder/resource_pool.cc | 20 +++++++-------
src/cpu/o3/commit_impl.hh | 24 +++++++++---------
src/cpu/o3/decode_impl.hh | 20 +++++++-------
src/cpu/o3/iew_impl.hh | 28 +++++++++++-----------
src/cpu/o3/inst_queue_impl.hh | 16 ++++++------
src/cpu/o3/rename_impl.hh | 42 ++++++++++++++++----------------
src/mem/cache/tags/base.cc | 2 +-
src/sim/process.cc | 2 +-
10 files changed, 103 insertions(+), 92 deletions(-)
diffs (truncated from 611 to 300 lines):
diff -r 24406820a7e0 -r 38befb82b2c9 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Tue Apr 19 11:13:01 2011 -0700
+++ b/src/cpu/inorder/pipeline_stage.cc Tue Apr 19 18:45:21 2011 -0700
@@ -88,7 +88,7 @@
std::string
PipelineStage::name() const
{
- return cpu->name() + ".stage-" + to_string(stageNum);
+ return cpu->name() + ".stage" + to_string(stageNum);
}
diff -r 24406820a7e0 -r 38befb82b2c9 src/cpu/inorder/resource_pool.9stage.cc
--- a/src/cpu/inorder/resource_pool.9stage.cc Tue Apr 19 11:13:01 2011 -0700
+++ b/src/cpu/inorder/resource_pool.9stage.cc Tue Apr 19 18:45:21 2011 -0700
@@ -48,37 +48,48 @@
// Declare Resource Objects
// name - id - bandwidth - latency - CPU - Parameters
// --------------------------------------------------
- resources.push_back(new FetchSeqUnit("Fetch-Seq-Unit", FetchSeq,
StageWidth * 2, 0, _cpu, params));
+ resources.push_back(new FetchSeqUnit("fetch_seq_unit", FetchSeq,
+ StageWidth * 2, 0, _cpu, params));
- resources.push_back(new TLBUnit("I-TLB", ITLB, StageWidth, 0, _cpu,
params));
+ resources.push_back(new TLBUnit("itlb", ITLB, StageWidth, 0, _cpu,
params));
memObjects.push_back(ICache);
- resources.push_back(new CacheUnit("icache_port", ICache, StageWidth *
MaxThreads, 0, _cpu, params));
+ resources.push_back(new CacheUnit("icache_port", ICache,
+ StageWidth * MaxThreads, 0, _cpu, params));
- resources.push_back(new DecodeUnit("Decode-Unit", Decode, StageWidth, 0,
_cpu, params));
+ resources.push_back(new DecodeUnit("decode_unit", Decode, StageWidth, 0,
+ _cpu, params));
- resources.push_back(new BranchPredictor("Branch-Predictor", BPred,
StageWidth, 0, _cpu, params));
+ resources.push_back(new BranchPredictor("branch_predictor", BPred,
+ StageWidth, 0, _cpu, params));
for (int i = 0; i < params->numberOfThreads; i++) {
char fbuff_name[20];
- sprintf(fbuff_name, "Fetch-Buffer-T%i", i);
- resources.push_back(new InstBuffer(fbuff_name, FetchBuff + i, 4, 0,
_cpu, params));
+ sprintf(fbuff_name, "fetch_buffer_t%i", i);
+ resources.push_back(new InstBuffer(fbuff_name, FetchBuff + i, 4, 0,
+ _cpu, params));
}
- resources.push_back(new UseDefUnit("RegFile-Manager", RegManager,
StageWidth * MaxThreads, 0, _cpu, params));
+ resources.push_back(new UseDefUnit("regfile_manager", RegManager,
+ StageWidth * MaxThreads, 0, _cpu, params));
- resources.push_back(new AGENUnit("AGEN-Unit", AGEN, StageWidth, 0, _cpu,
params));
+ resources.push_back(new AGENUnit("agen_unit", AGEN, StageWidth, 0, _cpu,
+ params));
- resources.push_back(new ExecutionUnit("Execution-Unit", ExecUnit,
StageWidth, 0, _cpu, params));
+ resources.push_back(new ExecutionUnit("execution_unit", ExecUnit,
+ StageWidth, 0, _cpu, params));
- resources.push_back(new MultDivUnit("Mult-Div-Unit", MDU, 5, 0, _cpu,
params));
+ resources.push_back(new MultDivUnit("mult_div_unit", MDU, 5, 0, _cpu,
+ params));
- resources.push_back(new TLBUnit("D-TLB", DTLB, StageWidth, 0, _cpu,
params));
+ resources.push_back(new TLBUnit("dtlb", DTLB, StageWidth, 0, _cpu,
params));
memObjects.push_back(DCache);
- resources.push_back(new CacheUnit("dcache_port", DCache, StageWidth *
MaxThreads, 0, _cpu, params));
+ resources.push_back(new CacheUnit("dcache_port", DCache,
+ StageWidth * MaxThreads, 0, _cpu, params));
- resources.push_back(new GraduationUnit("Graduation-Unit", Grad, StageWidth
* MaxThreads, 0, _cpu, params));
+ resources.push_back(new GraduationUnit("graduation_unit", Grad,
+ StageWidth * MaxThreads, 0, _cpu, params));
}
void
diff -r 24406820a7e0 -r 38befb82b2c9 src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc Tue Apr 19 11:13:01 2011 -0700
+++ b/src/cpu/inorder/resource_pool.cc Tue Apr 19 18:45:21 2011 -0700
@@ -51,7 +51,7 @@
// Declare Resource Objects
// name - id - bandwidth - latency - CPU - Parameters
// --------------------------------------------------
- resources.push_back(new FetchSeqUnit("Fetch-Seq-Unit", FetchSeq,
+ resources.push_back(new FetchSeqUnit("fetch_seq_unit", FetchSeq,
stage_width * 2, 0, _cpu, params));
memObjects.push_back(ICache);
@@ -59,26 +59,26 @@
stage_width * 2 + MaxThreads, 0, _cpu,
params));
- resources.push_back(new DecodeUnit("Decode-Unit", Decode,
+ resources.push_back(new DecodeUnit("decode_unit", Decode,
stage_width, 0, _cpu, params));
- resources.push_back(new BranchPredictor("Branch-Predictor", BPred,
+ resources.push_back(new BranchPredictor("branch_predictor", BPred,
stage_width, 0, _cpu, params));
- resources.push_back(new InstBuffer("Fetch-Buffer-T0", FetchBuff, 4,
+ resources.push_back(new InstBuffer("fetch_buffer_t0", FetchBuff, 4,
0, _cpu, params));
- resources.push_back(new UseDefUnit("RegFile-Manager", RegManager,
+ resources.push_back(new UseDefUnit("regfile_manager", RegManager,
stage_width * 3, 0, _cpu,
params));
- resources.push_back(new AGENUnit("AGEN-Unit", AGEN,
+ resources.push_back(new AGENUnit("agen_unit", AGEN,
stage_width, 0, _cpu, params));
- resources.push_back(new ExecutionUnit("Execution-Unit", ExecUnit,
+ resources.push_back(new ExecutionUnit("execution_unit", ExecUnit,
stage_width, 0, _cpu, params));
- resources.push_back(new MultDivUnit("Mult-Div-Unit", MDU,
+ resources.push_back(new MultDivUnit("mult_div_unit", MDU,
stage_width * 2, 0, _cpu, params));
memObjects.push_back(DCache);
@@ -86,11 +86,11 @@
stage_width * 2 + MaxThreads, 0, _cpu,
params));
- resources.push_back(new GraduationUnit("Graduation-Unit", Grad,
+ resources.push_back(new GraduationUnit("graduation_unit", Grad,
stage_width, 0, _cpu,
params));
- resources.push_back(new InstBuffer("Fetch-Buffer-T1", FetchBuff2, 4,
+ resources.push_back(new InstBuffer("fetch_buffer_t1", FetchBuff2, 4,
0, _cpu, params));
}
diff -r 24406820a7e0 -r 38befb82b2c9 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Tue Apr 19 11:13:01 2011 -0700
+++ b/src/cpu/o3/commit_impl.hh Tue Apr 19 18:45:21 2011 -0700
@@ -188,83 +188,83 @@
.prereq(branchMispredicts);
numCommittedDist
.init(0,commitWidth,1)
- .name(name() + ".COM:committed_per_cycle")
+ .name(name() + ".committed_per_cycle")
.desc("Number of insts commited each cycle")
.flags(Stats::pdf)
;
statComInst
.init(cpu->numThreads)
- .name(name() + ".COM:count")
+ .name(name() + ".count")
.desc("Number of instructions committed")
.flags(total)
;
statComSwp
.init(cpu->numThreads)
- .name(name() + ".COM:swp_count")
+ .name(name() + ".swp_count")
.desc("Number of s/w prefetches committed")
.flags(total)
;
statComRefs
.init(cpu->numThreads)
- .name(name() + ".COM:refs")
+ .name(name() + ".refs")
.desc("Number of memory references committed")
.flags(total)
;
statComLoads
.init(cpu->numThreads)
- .name(name() + ".COM:loads")
+ .name(name() + ".loads")
.desc("Number of loads committed")
.flags(total)
;
statComMembars
.init(cpu->numThreads)
- .name(name() + ".COM:membars")
+ .name(name() + ".membars")
.desc("Number of memory barriers committed")
.flags(total)
;
statComBranches
.init(cpu->numThreads)
- .name(name() + ".COM:branches")
+ .name(name() + ".branches")
.desc("Number of branches committed")
.flags(total)
;
statComFloating
.init(cpu->numThreads)
- .name(name() + ".COM:fp_insts")
+ .name(name() + ".fp_insts")
.desc("Number of committed floating point instructions.")
.flags(total)
;
statComInteger
.init(cpu->numThreads)
- .name(name()+".COM:int_insts")
+ .name(name()+".int_insts")
.desc("Number of committed integer instructions.")
.flags(total)
;
statComFunctionCalls
.init(cpu->numThreads)
- .name(name()+".COM:function_calls")
+ .name(name()+".function_calls")
.desc("Number of function calls committed.")
.flags(total)
;
commitEligible
.init(cpu->numThreads)
- .name(name() + ".COM:bw_limited")
+ .name(name() + ".bw_limited")
.desc("number of insts not committed due to BW limits")
.flags(total)
;
commitEligibleSamples
- .name(name() + ".COM:bw_lim_events")
+ .name(name() + ".bw_lim_events")
.desc("number cycles where commit BW limit reached")
;
}
diff -r 24406820a7e0 -r 38befb82b2c9 src/cpu/o3/decode_impl.hh
--- a/src/cpu/o3/decode_impl.hh Tue Apr 19 11:13:01 2011 -0700
+++ b/src/cpu/o3/decode_impl.hh Tue Apr 19 18:45:21 2011 -0700
@@ -77,44 +77,44 @@
DefaultDecode<Impl>::regStats()
{
decodeIdleCycles
- .name(name() + ".DECODE:IdleCycles")
+ .name(name() + ".IdleCycles")
.desc("Number of cycles decode is idle")
.prereq(decodeIdleCycles);
decodeBlockedCycles
- .name(name() + ".DECODE:BlockedCycles")
+ .name(name() + ".BlockedCycles")
.desc("Number of cycles decode is blocked")
.prereq(decodeBlockedCycles);
decodeRunCycles
- .name(name() + ".DECODE:RunCycles")
+ .name(name() + ".RunCycles")
.desc("Number of cycles decode is running")
.prereq(decodeRunCycles);
decodeUnblockCycles
- .name(name() + ".DECODE:UnblockCycles")
+ .name(name() + ".UnblockCycles")
.desc("Number of cycles decode is unblocking")
.prereq(decodeUnblockCycles);
decodeSquashCycles
- .name(name() + ".DECODE:SquashCycles")
+ .name(name() + ".SquashCycles")
.desc("Number of cycles decode is squashing")
.prereq(decodeSquashCycles);
decodeBranchResolved
- .name(name() + ".DECODE:BranchResolved")
+ .name(name() + ".BranchResolved")
.desc("Number of times decode resolved a branch")
.prereq(decodeBranchResolved);
decodeBranchMispred
- .name(name() + ".DECODE:BranchMispred")
+ .name(name() + ".BranchMispred")
.desc("Number of times decode detected a branch misprediction")
.prereq(decodeBranchMispred);
decodeControlMispred
- .name(name() + ".DECODE:ControlMispred")
+ .name(name() + ".ControlMispred")
.desc("Number of times decode detected an instruction incorrectly"
" predicted as a control")
.prereq(decodeControlMispred);
decodeDecodedInsts
- .name(name() + ".DECODE:DecodedInsts")
+ .name(name() + ".DecodedInsts")
.desc("Number of instructions handled by decode")
.prereq(decodeDecodedInsts);
decodeSquashedInsts
- .name(name() + ".DECODE:SquashedInsts")
+ .name(name() + ".SquashedInsts")
.desc("Number of squashed instructions handled by decode")
.prereq(decodeSquashedInsts);
}
diff -r 24406820a7e0 -r 38befb82b2c9 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Tue Apr 19 11:13:01 2011 -0700
+++ b/src/cpu/o3/iew_impl.hh Tue Apr 19 18:45:21 2011 -0700
@@ -194,36 +194,36 @@
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
