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src/mem/cache/base.hh <http://reviews.m5sim.org/r/654/#comment1564> This can pretty easily be done with a template: template <class STAT> void incThreadVectorStat(PacketPtr pkt, STAT &stat) { } I'm pretty sure that you could even do this: template <class STAT> STAT::Proxy & getThreadVectorStat(PacketPtr pkt, STAT &stat[]) { if (pkt->req->hasContextId()) { return stat[pkt->cmdToIndex()][pkt->req->contextId() % _numSharingContexts]; } else { assert(pkt->req->contextId() == -1); assert(FULL_SYSTEM); return stat[pkt->cmdToIndex()][_numSharingContexts]; } And do this: getThreadVectorStat(pkt, misses)++; getThreadVectorStat(pkt, misses) += 1; Actually, it may just be cleaner to have a function that returns the index. Then you don't need all of the template mubmo jumbo. src/mem/cache/base.hh <http://reviews.m5sim.org/r/654/#comment1566> _numSharingContexts has the + 1 in it for devices. Is that a problem? Seems like you need a parameter to know that. src/mem/cache/base.hh <http://reviews.m5sim.org/r/654/#comment1565> Maybe you can use a constant to indicate the -1 is a device. Also, let's make sure that you initialize to something other than -1. src/mem/cache/cache_impl.hh <http://reviews.m5sim.org/r/654/#comment1568> This makes me think that some sort of index function is the right way to go. src/mem/cache/cache_impl.hh <http://reviews.m5sim.org/r/654/#comment1569> Is it not possible to figure out which thread caused the wb? src/mem/cache/cache_impl.hh <http://reviews.m5sim.org/r/654/#comment1567> I think we should force context IDs to be set even by devices. src/mem/cache/cache_impl.hh <http://reviews.m5sim.org/r/654/#comment1570> Index function. - Nathan On 2011-04-22 17:16:05, Lisa Hsu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/654/ > ----------------------------------------------------------- > > (Updated 2011-04-22 17:16:05) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > Cache: fix vector stats in classic cache to have matching lengths > > > Diffs > ----- > > configs/common/CacheConfig.py 914389024c33 > src/cpu/base.cc 914389024c33 > src/mem/cache/BaseCache.py 914389024c33 > src/mem/cache/base.hh 914389024c33 > src/mem/cache/base.cc 914389024c33 > src/mem/cache/blk.hh 914389024c33 > src/mem/cache/cache_impl.hh 914389024c33 > src/mem/cache/tags/base.cc 914389024c33 > src/mem/cache/tags/lru.cc 914389024c33 > > Diff: http://reviews.m5sim.org/r/654/diff > > > Testing > ------- > > > Thanks, > > Lisa > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
