changeset 7226aebb77b4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7226aebb77b4
description:
network: convert links & switches to first class C++ SimObjects
This patch converts links and switches from second class simobjects
that were
virtually ignored by the networks (both simple and Garnet) to first
class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet,
where the
links and switches directly correspond to specific C++ objects.
By making this change, many aspects of the Topology class were
simplified.
diffstat:
configs/ruby/MESI_CMP_directory.py | 14 +
configs/ruby/MI_example.py | 11 +
configs/ruby/MOESI_CMP_directory.py | 14 +
configs/ruby/MOESI_CMP_token.py | 14 +
configs/ruby/MOESI_hammer.py | 11 +
configs/ruby/Network_test.py | 8 +
configs/ruby/Ruby.py | 34 +-
src/mem/protocol/RubySlicc_Exports.sm | 6 +
src/mem/ruby/network/BasicLink.cc | 80 +++
src/mem/ruby/network/BasicLink.hh | 96 ++++
src/mem/ruby/network/BasicLink.py | 50 ++
src/mem/ruby/network/BasicRouter.cc | 52 ++
src/mem/ruby/network/BasicRouter.hh | 67 +++
src/mem/ruby/network/BasicRouter.py | 35 +
src/mem/ruby/network/Network.hh | 22 +-
src/mem/ruby/network/Network.py | 25 +-
src/mem/ruby/network/SConscript | 4 +
src/mem/ruby/network/Topology.cc | 216 ++++-----
src/mem/ruby/network/Topology.hh | 58 +-
src/mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh | 6 +-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc | 83 +++
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh | 92 ++++
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py | 85 +++
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc | 79 ++-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh | 21 +-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py | 44 ++
src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc | 30 +-
src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh | 10 +-
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc | 23 +-
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh | 13 +-
src/mem/ruby/network/garnet/fixed-pipeline/SConscript | 3 +
src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc | 78 +++
src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh | 89 ++++
src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py | 68 +++
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc | 61 +-
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh | 24 +-
src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py | 44 ++
src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc | 18 +-
src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh | 13 +-
src/mem/ruby/network/garnet/flexible-pipeline/Router.cc | 18 +-
src/mem/ruby/network/garnet/flexible-pipeline/Router.hh | 12 +-
src/mem/ruby/network/garnet/flexible-pipeline/SConscript | 3 +
src/mem/ruby/network/orion/NetworkPower.cc | 13 +-
src/mem/ruby/network/simple/SimpleNetwork.cc | 30 +-
src/mem/ruby/network/simple/SimpleNetwork.hh | 21 +-
src/mem/ruby/network/topologies/Crossbar.py | 17 +-
src/mem/ruby/network/topologies/Mesh.py | 32 +-
src/mem/ruby/network/topologies/MeshDirCorners.py | 50 +-
src/mem/ruby/slicc_interface/AbstractController.hh | 1 +
src/mem/ruby/slicc_interface/Controller.py | 1 +
50 files changed, 1531 insertions(+), 368 deletions(-)
diffs (truncated from 3122 to 300 lines):
diff -r 2284cec55ef4 -r 7226aebb77b4 configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py Thu Apr 28 17:18:12 2011 -0700
+++ b/configs/ruby/MESI_CMP_directory.py Thu Apr 28 17:18:14 2011 -0700
@@ -71,6 +71,8 @@
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
+ cntrl_count = 0
+
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
@@ -92,6 +94,7 @@
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
@@ -104,6 +107,8 @@
#
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+
+ cntrl_count += 1
l2_index_start = block_size_bits + l2_bits
@@ -116,11 +121,14 @@
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
L2cacheMemory = l2_cache)
exec("system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+ cntrl_count += 1
+
phys_mem_size = long(system.physmem.range.second) - \
long(system.physmem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
@@ -136,6 +144,7 @@
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
+ cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory(version = i,
size = \
@@ -145,6 +154,8 @@
exec("system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ cntrl_count += 1
+
for i, dma_device in enumerate(dma_devices):
#
# Create the Ruby objects associated with the dma controller
@@ -154,6 +165,7 @@
physmem = system.physmem)
dma_cntrl = DMA_Controller(version = i,
+ cntrl_id = cntrl_count,
dma_sequencer = dma_seq)
exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -163,6 +175,8 @@
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ cntrl_count += 1
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
diff -r 2284cec55ef4 -r 7226aebb77b4 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Thu Apr 28 17:18:12 2011 -0700
+++ b/configs/ruby/MI_example.py Thu Apr 28 17:18:14 2011 -0700
@@ -62,6 +62,8 @@
# controller constructors are called before the network constructor
#
block_size_bits = int(math.log(options.cacheline_size, 2))
+
+ cntrl_count = 0
for i in xrange(options.num_cpus):
#
@@ -86,6 +88,7 @@
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
sequencer = cpu_seq,
cacheMemory = cache)
@@ -96,6 +99,8 @@
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ cntrl_count += 1
+
phys_mem_size = long(system.physmem.range.second) - \
long(system.physmem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
@@ -111,6 +116,7 @@
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
+ cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory( \
version = i,
@@ -123,6 +129,8 @@
exec("system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ cntrl_count += 1
+
for i, dma_device in enumerate(dma_devices):
#
# Create the Ruby objects associated with the dma controller
@@ -132,6 +140,7 @@
physmem = system.physmem)
dma_cntrl = DMA_Controller(version = i,
+ cntrl_id = cntrl_count,
dma_sequencer = dma_seq)
exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -142,6 +151,8 @@
dma_cntrl.dma_sequencer.port = dma_device.dma
dma_cntrl_nodes.append(dma_cntrl)
+ cntrl_count += 1
+
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
diff -r 2284cec55ef4 -r 7226aebb77b4 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py Thu Apr 28 17:18:12 2011 -0700
+++ b/configs/ruby/MOESI_CMP_directory.py Thu Apr 28 17:18:14 2011 -0700
@@ -70,6 +70,8 @@
#
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
+
+ cntrl_count = 0
for i in xrange(options.num_cpus):
#
@@ -92,6 +94,7 @@
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
@@ -104,6 +107,8 @@
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ cntrl_count += 1
+
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -115,10 +120,13 @@
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
L2cacheMemory = l2_cache)
exec("system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+
+ cntrl_count += 1
phys_mem_size = long(system.physmem.range.second) - \
long(system.physmem.range.first) + 1
@@ -135,6 +143,7 @@
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
+ cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory(version = i,
size = \
@@ -144,6 +153,8 @@
exec("system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ cntrl_count += 1
+
for i, dma_device in enumerate(dma_devices):
#
# Create the Ruby objects associated with the dma controller
@@ -153,6 +164,7 @@
physmem = system.physmem)
dma_cntrl = DMA_Controller(version = i,
+ cntrl_id = cntrl_count,
dma_sequencer = dma_seq)
exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -162,6 +174,8 @@
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ cntrl_count += 1
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
diff -r 2284cec55ef4 -r 7226aebb77b4 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py Thu Apr 28 17:18:12 2011 -0700
+++ b/configs/ruby/MOESI_CMP_token.py Thu Apr 28 17:18:14 2011 -0700
@@ -84,6 +84,8 @@
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
+ cntrl_count = 0
+
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
@@ -105,6 +107,7 @@
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
@@ -126,6 +129,8 @@
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ cntrl_count += 1
+
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -137,11 +142,14 @@
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
L2cacheMemory = l2_cache,
N_tokens = n_tokens)
exec("system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+
+ cntrl_count += 1
phys_mem_size = long(system.physmem.range.second) - \
long(system.physmem.range.first) + 1
@@ -158,6 +166,7 @@
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
+ cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory(version = i,
size = \
@@ -168,6 +177,8 @@
exec("system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ cntrl_count += 1
+
for i, dma_device in enumerate(dma_devices):
#
# Create the Ruby objects associated with the dma controller
@@ -177,6 +188,7 @@
physmem = system.physmem)
dma_cntrl = DMA_Controller(version = i,
+ cntrl_id = cntrl_count,
dma_sequencer = dma_seq)
exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -186,6 +198,8 @@
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ cntrl_count += 1
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
diff -r 2284cec55ef4 -r 7226aebb77b4 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Thu Apr 28 17:18:12 2011 -0700
+++ b/configs/ruby/MOESI_hammer.py Thu Apr 28 17:18:14 2011 -0700
@@ -79,6 +79,8 @@
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