> On 2011-05-03 11:13:49, Gabe Black wrote: > > Could you please walk through when two faults will happen at the same time > > and why that's a problem? > > Ali Saidi wrote: > > mem op -> tlb miss -> delayed translation -> table walk -> fault -> fetch > -> tlb miss -> table walk > > The table walker should never be called twice in one cycle. After the > first fault we really want to unwind the call stack, let a cycle go by, and > then start fetching handling the next instruction. > > These cases generate traces that are super hard to debug, unrealistic, > and make debugging challenging so we should avoid them.
Ah, ok. I think this is similar to that problem where the call stack wraps back around on itself too many times and tracedata gets deleted out from under an earlier frame by a later frame. It's good to break that cycle here, I think. I didn't see anything (other than my comment below) that was objectionable, so if you've tested it go ahead. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/670/#review1190 ----------------------------------------------------------- On 2011-05-02 15:41:43, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/670/ > ----------------------------------------------------------- > > (Updated 2011-05-02 15:41:43) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > CPU: Fix a case where timing simple cpu faults can nest. > > If we fault, change the state to faulting so that we don't fault again in the > same cycle. > > > Diffs > ----- > > src/cpu/simple/base.hh 3f49ed206f46 > src/cpu/simple/timing.cc 3f49ed206f46 > > Diff: http://reviews.m5sim.org/r/670/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
