changeset 66bb0d8ae8bf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=66bb0d8ae8bf
description:
CPU: Fix a case where timing simple cpu faults can nest.
If we fault, change the state to faulting so that we don't fault again
in the same cycle.
diffstat:
src/cpu/simple/base.hh | 1 +
src/cpu/simple/timing.cc | 21 ++++++++++++++++-----
2 files changed, 17 insertions(+), 5 deletions(-)
diffs (63 lines):
diff -r 8c88a94c2f4f -r 66bb0d8ae8bf src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh Wed May 04 20:38:27 2011 -0500
+++ b/src/cpu/simple/base.hh Wed May 04 20:38:27 2011 -0500
@@ -124,6 +124,7 @@
enum Status {
Idle,
Running,
+ Faulting,
ITBWaitResponse,
IcacheRetry,
IcacheWaitResponse,
diff -r 8c88a94c2f4f -r 66bb0d8ae8bf src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Wed May 04 20:38:27 2011 -0500
+++ b/src/cpu/simple/timing.cc Wed May 04 20:38:27 2011 -0500
@@ -725,6 +725,7 @@
bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
if (needToFetch) {
+ _status = Running;
Request *ifetch_req = new Request();
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
setupFetchRequest(ifetch_req);
@@ -771,7 +772,20 @@
void
TimingSimpleCPU::advanceInst(Fault fault)
{
- if (fault != NoFault || !stayAtPC)
+
+ if (_status == Faulting)
+ return;
+
+ if (fault != NoFault) {
+ advancePC(fault);
+ DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
+ reschedule(fetchEvent, nextCycle(), true);
+ _status = Faulting;
+ return;
+ }
+
+
+ if (!stayAtPC)
advancePC(fault);
if (_status == Running) {
@@ -786,8 +800,6 @@
void
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
- DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
-
// received a response from the icache: execute the received
// instruction
@@ -878,8 +890,7 @@
tickEvent.schedule(pkt, next_tick);
return true;
- }
- else if (pkt->wasNacked()) {
+ } else if (pkt->wasNacked()) {
assert(cpu->_status == IcacheWaitResponse);
pkt->reinitNacked();
if (!sendTiming(pkt)) {
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