changeset e169269a1829 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e169269a1829
description:
O3/ARM: Update stats for recent changes.
diffstat:
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 4 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
| 10 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 984 +++++-----
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
| 2 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
| 0
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
| 2 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
| 8 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 770 +++---
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
| 8 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 669 +++---
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 4 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 362 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 4 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 548 ++--
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
| 0
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
| 2 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
| 8 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
| 880 ++++----
22 files changed, 2144 insertions(+), 2143 deletions(-)
diffs (truncated from 5490 to 300 lines):
diff -r 4fe5f7f5094c -r e169269a1829
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini Wed May
04 20:38:27 2011 -0500
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini Wed May
04 20:38:27 2011 -0500
@@ -11,7 +11,7 @@
boot_cpu_frequency=500
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8
mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:-
root=/dev/mtdblock0
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@@ -495,7 +495,7 @@
[system.diskmem]
type=PhysicalMemory
-file=/dist/m5/system/disks/ael-arm.ext2
+file=/chips/pd/randd/dist/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false
diff -r 4fe5f7f5094c -r e169269a1829
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout Wed May 04
20:38:27 2011 -0500
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout Wed May 04
20:38:27 2011 -0500
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Apr 21 2011 12:05:49
-M5 started Apr 21 2011 15:19:16
-M5 executing on maize
+M5 compiled May 1 2011 21:51:08
+M5 started May 1 2011 21:52:01
+M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.fast -d
build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re
tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 82662490500 because m5_exit instruction encountered
+Exiting @ tick 82642207500 because m5_exit instruction encountered
diff -r 4fe5f7f5094c -r e169269a1829
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Wed May
04 20:38:27 2011 -0500
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Wed May
04 20:38:27 2011 -0500
@@ -1,430 +1,430 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 112653 #
Simulator instruction rate (inst/s)
-host_mem_usage 348660 #
Number of bytes of host memory used
-host_seconds 461.40 #
Real time elapsed on the host
-host_tick_rate 179154205 #
Simulator tick rate (ticks/s)
+host_inst_rate 118050 #
Simulator instruction rate (inst/s)
+host_mem_usage 388868 #
Number of bytes of host memory used
+host_seconds 439.34 #
Real time elapsed on the host
+host_tick_rate 188104852 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 51978682 #
Number of instructions simulated
-sim_seconds 0.082662 #
Number of seconds simulated
-sim_ticks 82662490500 #
Number of ticks simulated
+sim_insts 51864248 #
Number of instructions simulated
+sim_seconds 0.082642 #
Number of seconds simulated
+sim_ticks 82642207500 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 9175263 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 11695749 #
Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 155381 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 665245 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 11246732 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 13229511 #
Number of BP lookups
-system.cpu.BPredUnit.usedRAS 787550 #
Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts 641726 #
The number of times a branch was mispredicted
-system.cpu.commit.branches 8445621 #
Number of branches committed
-system.cpu.commit.bw_lim_events 801383 #
number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits 9217139 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 11723346 #
Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 156768 #
Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 663592 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 11213737 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 13194323 #
Number of BP lookups
+system.cpu.BPredUnit.usedRAS 788661 #
Number of times the RAS was used to get a target.
+system.cpu.commit.branchMispredicts 639897 #
The number of times a branch was mispredicted
+system.cpu.commit.branches 8427507 #
Number of branches committed
+system.cpu.commit.bw_lim_events 797883 #
number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts 52101862 #
The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 2963383 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 16147201 #
The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples 93507712
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.557193
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.351787
# Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 51987478 #
The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 2962739 #
The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 16084299 #
The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples 93469913
# Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.556195
# Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.349609
# Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 71892468 76.88% 76.88% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 10568988 11.30% 88.19% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3427833 3.67% 91.85% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1711600 1.83% 93.68% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3527395 3.77% 97.46% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 741726 0.79% 98.25% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 541099 0.58% 98.83% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 295220 0.32% 99.14% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 801383 0.86% 100.00% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 71838189 76.86% 76.86% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 10610207 11.35% 88.21% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3480363 3.72% 91.93% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 1644006 1.76% 93.69% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 3523448 3.77% 97.46% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 741299 0.79% 98.25% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 540450 0.58% 98.83% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 294068 0.31% 99.15% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 797883 0.85% 100.00% #
Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 93507712
# Number of insts commited each cycle
-system.cpu.commit.count 52101862 #
Number of instructions committed
+system.cpu.commit.committed_per_cycle::total 93469913
# Number of insts commited each cycle
+system.cpu.commit.count 51987478 #
Number of instructions committed
system.cpu.commit.fp_insts 6017 #
Number of committed floating point instructions.
-system.cpu.commit.function_calls 529734 #
Number of function calls committed.
-system.cpu.commit.int_insts 42509491 #
Number of committed integer instructions.
-system.cpu.commit.loads 9207015 #
Number of loads committed
+system.cpu.commit.function_calls 529811 #
Number of function calls committed.
+system.cpu.commit.int_insts 42411675 #
Number of committed integer instructions.
+system.cpu.commit.loads 9176268 #
Number of loads committed
system.cpu.commit.membars 3 #
Number of memory barriers committed
-system.cpu.commit.refs 16293738 #
Number of memory references committed
+system.cpu.commit.refs 16251703 #
Number of memory references committed
system.cpu.commit.swp_count 0 #
Number of s/w prefetches committed
-system.cpu.committedInsts 51978682 #
Number of Instructions Simulated
-system.cpu.committedInsts_total 51978682 #
Number of Instructions Simulated
-system.cpu.cpi 3.180631 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.180631 #
CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses::0 111504
# number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 111504
# number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14941.207869
# average LoadLockedReq miss latency
+system.cpu.committedInsts 51864248 #
Number of Instructions Simulated
+system.cpu.committedInsts_total 51864248 #
Number of Instructions Simulated
+system.cpu.cpi 3.186866 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.186866 #
CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses::0 111590
# number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 111590
# number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14996.059342
# average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf
# average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf
# average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11805.277281
# average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0 104947 #
number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 104947
# number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 97969500
# number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058805
# miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 6557 #
number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 6557
# number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits 967 #
number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65991500
# number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050133
# mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11857.982282
# average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0 105119 #
number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 105119
# number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 97039500
# number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.057989
# miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 6471 #
number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 6471
# number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits 940 #
number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65586500
# number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049565
# mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf
# mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf
# mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 5590
# number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 9423338 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9423338 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 14823.280125
# average ReadReq miss latency
+system.cpu.dcache.LoadLockedReq_mshr_misses 5531
# number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses::0 9392794 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9392794 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 14764.348504
# average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf
# average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13267.626376
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13258.945954
# average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf
# average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 8937009 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 8937009 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 7208991000 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.051609 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 486329 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 486329 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 237469 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3301781500
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026409
# mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0 8903858 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 8903858 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 7218821500 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0 0.052054 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 488936 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 488936 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 240332 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3296227000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026468
# mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf
# mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf
# mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 248860 #
number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38194393000
# number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 105004
# number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 105004
# number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 105004 #
number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 105004
# number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6672578 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6672578
# number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 39930.375248
# average WriteReq miss latency
+system.cpu.dcache.ReadReq_mshr_misses 248604 #
number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38194550500
# number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0 105035
# number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 105035
# number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0 105035 #
number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 105035
# number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0 6661106 #
number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6661106
# number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 39940.947710
# average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf
# average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38504.296551
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38496.257162
# average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf
# average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 4626571 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4626571 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 81697827271 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.306629 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 2046007 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2046007 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1875409 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 6568755983
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025567
# mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0 4616668 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4616668 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 81656791255 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0 0.306922 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 2044438 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2044438 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1873841 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 6567345983
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025611
# mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf
# mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf
# mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 170598 #
number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 940173192
# number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7672.355023
# average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 21291.666667
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 32.542596 #
Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 876 #
number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 24 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 6720983
# number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 511000
# number of cycles access was blocked
+system.cpu.dcache.WriteReq_mshr_misses 170597 #
number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 940602193
# number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 7422.728541
# average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 22666.666667
# average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 32.464127 #
Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 932 #
number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 30 #
number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 6917983
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 680000
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses::0 16095916 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0 16053900 #
number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 16095916 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 35108.618395
# average overall miss latency
+system.cpu.dcache.demand_accesses::total 16053900 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 35081.915562
# average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf
# average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf
# average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23531.646751
# average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 13563580 #
number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 23529.459574
# average overall mshr miss latency
+system.cpu.dcache.demand_hits::0 13520526 #
number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 #
number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13563580 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 88906818271 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.157328 #
miss rate for demand accesses
+system.cpu.dcache.demand_hits::total 13520526 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 88875612755 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0 0.157804 #
miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value #
miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value #
miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 2532336 #
number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 2533374 #
number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 #
number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2532336 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2112878 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9870537483
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.026060
# mshr miss rate for demand accesses
+system.cpu.dcache.demand_misses::total 2533374 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2114173 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 9863572983
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0.026112
# mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf
# mshr miss rate for demand accesses
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