changeset 5a95f1d2494e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5a95f1d2494e
description:
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are
individually
written and this removes some incorrect dependencies between
instructions.
diffstat:
src/arch/arm/faults.cc | 9 ++++--
src/arch/arm/intregs.hh | 4 ++-
src/arch/arm/isa/formats/fp.isa | 8 +-----
src/arch/arm/isa/formats/pred.isa | 36 ++++++++++++++-------------
src/arch/arm/isa/insts/data.isa | 42 ++++++++++++++++++++------------
src/arch/arm/isa/insts/fp.isa | 16 ++++++-----
src/arch/arm/isa/insts/ldr.isa | 8 ++++-
src/arch/arm/isa/insts/macromem.isa | 40 ++++++++++++++++++------------
src/arch/arm/isa/insts/mem.isa | 31 +++++++++++++++++++++--
src/arch/arm/isa/insts/misc.isa | 48 +++++++++++++++++++++++++-----------
src/arch/arm/isa/insts/mult.isa | 2 +-
src/arch/arm/isa/insts/str.isa | 2 +-
src/arch/arm/isa/operands.isa | 21 +++++++++++++---
src/arch/arm/isa/templates/pred.isa | 4 +-
src/arch/arm/isa/templates/vfp.isa | 4 +++
src/arch/arm/miscregs.hh | 5 +---
src/arch/arm/nativetrace.cc | 10 +++++--
src/arch/arm/utility.hh | 33 +++++++++++++-----------
18 files changed, 206 insertions(+), 117 deletions(-)
diffs (truncated from 646 to 300 lines):
diff -r 9f23d01421de -r 5a95f1d2494e src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/faults.cc Fri May 13 17:27:01 2011 -0500
@@ -106,9 +106,12 @@
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
- CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
- tc->readIntReg(INTREG_CONDCODES_F) |
- tc->readIntReg(INTREG_CONDCODES_GE);
+ CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
+ saved_cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
+ saved_cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
+ saved_cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
+ saved_cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
+
Addr curPc M5_VAR_USED = tc->pcState().pc();
ITSTATE it = tc->pcState().itstate();
saved_cpsr.it2 = it.top6;
diff -r 9f23d01421de -r 5a95f1d2494e src/arch/arm/intregs.hh
--- a/src/arch/arm/intregs.hh Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/intregs.hh Fri May 13 17:27:01 2011 -0500
@@ -112,7 +112,9 @@
INTREG_UREG0,
INTREG_UREG1,
INTREG_UREG2,
- INTREG_CONDCODES_F,
+ INTREG_CONDCODES_NZ,
+ INTREG_CONDCODES_C,
+ INTREG_CONDCODES_V,
INTREG_CONDCODES_GE,
INTREG_FPCONDCODES,
diff -r 9f23d01421de -r 5a95f1d2494e src/arch/arm/isa/formats/fp.isa
--- a/src/arch/arm/isa/formats/fp.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/formats/fp.isa Fri May 13 17:27:01 2011 -0500
@@ -2068,14 +2068,8 @@
return new Unknown(machInst);
}
if (rt == 0xf) {
- CPSR cpsrMask = 0;
- cpsrMask.n = 1;
- cpsrMask.z = 1;
- cpsrMask.c = 1;
- cpsrMask.v = 1;
if (specReg == MISCREG_FPSCR) {
- return new VmrsApsrFpscr(machInst, INTREG_CONDCODES_F,
- (IntRegIndex)specReg, (uint32_t)cpsrMask);
+ return new VmrsApsrFpscr(machInst);
} else {
return new Unknown(machInst);
}
diff -r 9f23d01421de -r 5a95f1d2494e src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/formats/pred.isa Fri May 13 17:27:01 2011 -0500
@@ -53,7 +53,9 @@
_iv = %(ivValue)s & 1;
_ic = %(icValue)s & 1;
- CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28;
+ CondCodesNZ = (_in << 1) | (_iz);
+ CondCodesC = _ic;
+ CondCodesV = _iv;
DPRINTF(Arm, "in = %%d\\n", _in);
DPRINTF(Arm, "iz = %%d\\n", _iz);
@@ -70,11 +72,11 @@
canOverflow = 'false'
if flagtype == "none":
- icReg = icImm = 'CondCodesF<29:>'
- iv = 'CondCodesF<28:>'
+ icReg = icImm = 'CondCodesC'
+ iv = 'CondCodesV'
elif flagtype == "llbit":
- icReg = icImm = 'CondCodesF<29:>'
- iv = 'CondCodesF<28:>'
+ icReg = icImm = 'CondCodesC'
+ iv = 'CondCodesV'
negBit = 63
elif flagtype == "overflow":
canOverflow = "true"
@@ -89,9 +91,9 @@
icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
iv = 'findOverflow(32, resTemp, op2, ~Rn)'
else:
- icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesF<29:>)'
- icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesF<29:>)'
- iv = 'CondCodesF<28:>'
+ icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)'
+ icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)'
+ iv = 'CondCodesV'
return (calcCcCode % {"icValue" : icReg,
"ivValue" : iv,
"negBit" : negBit,
@@ -106,11 +108,11 @@
negBit = 31
canOverflow = 'false'
if flagtype == "none":
- icValue = 'CondCodesF<29:>'
- ivValue = 'CondCodesF<28:>'
+ icValue = 'CondCodesC'
+ ivValue = 'CondCodesV'
elif flagtype == "llbit":
- icValue = 'CondCodesF<29:>'
- ivValue = 'CondCodesF<28:>'
+ icValue = 'CondCodesC'
+ ivValue = 'CondCodesV'
negBit = 63
elif flagtype == "overflow":
icVaule = ivValue = '0'
@@ -126,20 +128,20 @@
ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
elif flagtype == "modImm":
icValue = 'rotated_carry'
- ivValue = 'CondCodesF<28:>'
+ ivValue = 'CondCodesV'
else:
- icValue = '(rotate ? rotated_carry:CondCodesF<29:>)'
- ivValue = 'CondCodesF<28:>'
+ icValue = '(rotate ? rotated_carry:CondCodesC)'
+ ivValue = 'CondCodesV'
return calcCcCode % vars()
}};
def format DataOp(code, flagtype = logic) {{
(regCcCode, immCcCode) = getCcCode(flagtype)
regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
- shift, CondCodesF<29:>);
+ shift, CondCodesC);
op2 = op2;''' + code
immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
- shift, CondCodesF<29:>);
+ shift, CondCodesC);
op2 = op2;''' + code
regIop = InstObjParams(name, Name, 'PredIntOp',
{"code": regCode,
diff -r 9f23d01421de -r 5a95f1d2494e src/arch/arm/isa/insts/data.isa
--- a/src/arch/arm/isa/insts/data.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/data.isa Fri May 13 17:27:01 2011 -0500
@@ -44,7 +44,7 @@
exec_output = ""
calcGECode = '''
- CondCodesGE = insertBits(0, 19, 16, resTemp);
+ CondCodesGE = resTemp;
'''
calcQCode = '''
@@ -58,15 +58,17 @@
_iv = %(ivValue)s & 1;
_ic = %(icValue)s & 1;
- CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28;
+ CondCodesNZ = (_in << 1) | _iz;
+ CondCodesC = _ic;
+ CondCodesV = _iv;
DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
_in, _iz, _ic, _iv);
'''
# Dict of code to set the carry flag. (imm, reg, reg-reg)
- oldC = 'CondCodesF<29:>'
- oldV = 'CondCodesF<28:>'
+ oldC = 'CondCodesC'
+ oldV = 'CondCodesV'
carryCode = {
"none": (oldC, oldC, oldC),
"llbit": (oldC, oldC, oldC),
@@ -101,8 +103,8 @@
secondOpRe = re.compile("secondOp")
immOp2 = "imm"
- regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesF<29:>)"
- regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesF<29:>)"
+ regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)"
+ regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)"
def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
buildCc = True, buildNonCc = True, instFlags = []):
@@ -238,16 +240,24 @@
if subsPcLr:
code += '''
SCTLR sctlr = Sctlr;
- uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE,
- Spsr, 0xF, true, sctlr.nmfi);
- Cpsr = ~CondCodesMask & newCpsr;
- CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesGE = CondCodesMaskGE & newCpsr;
- NextThumb = ((CPSR)newCpsr).t;
- NextJazelle = ((CPSR)newCpsr).j;
- NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
- | (((CPSR)newCpsr).it1 & 0x3);
+ CPSR old_cpsr = Cpsr;
+ old_cpsr.nz = CondCodesNZ;
+ old_cpsr.c = CondCodesC;
+ old_cpsr.v = CondCodesV;
+ old_cpsr.ge = CondCodesGE;
+
+ CPSR new_cpsr =
+ cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & new_cpsr;
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
+
+ NextThumb = (new_cpsr).t;
+ NextJazelle = (new_cpsr).j;
+ NextItState = (((new_cpsr).it2 << 2) & 0xFC)
+ | ((new_cpsr).it1 & 0x3);
SevMailbox = 1;
'''
buildImmDataInst(mnem + 's', code, flagType,
diff -r 9f23d01421de -r 5a95f1d2494e src/arch/arm/isa/insts/fp.isa
--- a/src/arch/arm/isa/insts/fp.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/fp.isa Fri May 13 17:27:01 2011 -0500
@@ -235,16 +235,18 @@
decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
exec_output += PredOpExecute.subst(vmrsFpscrIop);
- vmrsApsrFpscrCode = vmrsEnabledCheckCode + '''
- Dest = FpCondCodes & FpCondCodesMask;
+ vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + '''
+ FPSCR fpscr = FpCondCodes;
+ CondCodesNZ = (fpscr.n << 1) | fpscr.z;
+ CondCodesC = fpscr.c;
+ CondCodesV = fpscr.v;
'''
- vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp",
+ vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp",
{ "code": vmrsApsrFpscrCode,
"predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" },
- ["IsSerializeBefore"])
- header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop);
- decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop);
+ "op_class": "SimdFloatMiscOp" })
+ header_output += BasicDeclare.subst(vmrsApsrFpscrIop);
+ decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop);
exec_output += PredOpExecute.subst(vmrsApsrFpscrIop);
vmovImmSCode = vfpEnabledCheckCode + '''
diff -r 9f23d01421de -r 5a95f1d2494e src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/ldr.isa Fri May 13 17:27:01 2011 -0500
@@ -106,7 +106,11 @@
wbDiff = 8
accCode = '''
CPSR cpsr = Cpsr;
- URc = cpsr | CondCodesF | CondCodesGE;
+ cpsr.nz = CondCodesNZ;
+ cpsr.c = CondCodesC;
+ cpsr.v = CondCodesV;
+ cpsr.ge = CondCodesGE;
+ URc = cpsr;
URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
'''
@@ -137,7 +141,7 @@
def __init__(self, *args, **kargs):
super(LoadRegInst, self).__init__(*args, **kargs)
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
- " shiftType, CondCodesF<29:>)"
+ " shiftType, CondCodesC)"
if self.add:
self.wbDecl = '''
MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt,
shiftType);
diff -r 9f23d01421de -r 5a95f1d2494e src/arch/arm/isa/insts/macromem.isa
--- a/src/arch/arm/isa/insts/macromem.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/macromem.isa Fri May 13 17:27:01 2011 -0500
@@ -87,15 +87,21 @@
['IsMicroop'])
microRetUopCode = '''
- CPSR cpsr = Cpsr;
+ CPSR old_cpsr = Cpsr;
SCTLR sctlr = Sctlr;
- uint32_t newCpsr =
- cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE,
- Spsr, 0xF, true, sctlr.nmfi);
- Cpsr = ~CondCodesMask & newCpsr;
- CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesGE = CondCodesMaskGE & newCpsr;
- IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
+ old_cpsr.nz = CondCodesNZ;
+ old_cpsr.c = CondCodesC;
+ old_cpsr.v = CondCodesV;
+ old_cpsr.ge = CondCodesGE;
+
+ CPSR new_cpsr =
+ cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & new_cpsr;
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
+ IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
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