Why not just let TraceFlags be interpreted as DebugFlags, so TraceFlags still works for users.
On 3 Jun 2011, at 02:08, Nathan Binkert wrote: > changeset 9228e00459d4 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=9228e00459d4 > description: > scons: rename TraceFlags to DebugFlags > > diffstat: > > src/SConscript | 2 - > src/arch/SConscript | 6 +- > src/arch/arm/SConscript | 8 ++-- > src/arch/mips/SConscript | 2 +- > src/arch/power/SConscript | 2 +- > src/arch/sparc/SConscript | 4 +- > src/arch/x86/SConscript | 10 +++--- > src/base/SConscript | 24 +++++++------- > src/base/vnc/SConscript | 2 +- > src/cpu/SConscript | 54 ++++++++++++++++---------------- > src/cpu/inorder/SConscript | 44 +++++++++++++------------- > src/cpu/o3/SConscript | 24 +++++++------- > src/cpu/ozone/SConscript | 10 +++--- > src/cpu/pred/SConscript | 2 +- > src/cpu/simple/SConscript | 2 +- > src/cpu/testers/directedtest/SConscript | 2 +- > src/cpu/testers/memtest/SConscript | 2 +- > src/cpu/testers/networktest/SConscript | 2 +- > src/cpu/testers/rubytest/SConscript | 2 +- > src/dev/SConscript | 50 +++++++++++++++--------------- > src/dev/alpha/SConscript | 4 +- > src/dev/arm/SConscript | 8 ++-- > src/dev/mips/SConscript | 2 +- > src/dev/sparc/SConscript | 2 +- > src/dev/x86/SConscript | 16 ++++---- > src/kern/SConscript | 6 +- > src/mem/SConscript | 34 ++++++++++---------- > src/mem/cache/SConscript | 8 ++-- > src/mem/cache/tags/SConscript | 4 +- > src/sim/SConscript | 34 ++++++++++---------- > 30 files changed, 185 insertions(+), 187 deletions(-) > > diffs (truncated from 687 to 300 lines): > > diff -r 483e936f44f0 -r 9228e00459d4 src/SConscript > --- a/src/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -270,7 +270,6 @@ > if name in debug_flags: > raise AttributeError, "Flag %s already specified" % name > debug_flags[name] = (name, (), desc) > -TraceFlag = DebugFlag > > def CompoundFlag(name, flags, desc=None): > if name in debug_flags: > @@ -280,7 +279,6 @@ > debug_flags[name] = (name, compound, desc) > > Export('DebugFlag') > -Export('TraceFlag') > Export('CompoundFlag') > > ######################################################################## > diff -r 483e936f44f0 -r 9228e00459d4 src/arch/SConscript > --- a/src/arch/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/arch/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -126,7 +126,7 @@ > > env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) > > -TraceFlag('IntRegs') > -TraceFlag('FloatRegs') > -TraceFlag('MiscRegs') > +DebugFlag('IntRegs') > +DebugFlag('FloatRegs') > +DebugFlag('MiscRegs') > CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ]) > diff -r 483e936f44f0 -r 9228e00459d4 src/arch/arm/SConscript > --- a/src/arch/arm/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/arch/arm/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -65,10 +65,10 @@ > SimObject('ArmNativeTrace.py') > SimObject('ArmTLB.py') > > - TraceFlag('Arm') > - TraceFlag('TLBVerbose') > - TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi") > - TraceFlag('Predecoder', "Instructions returned by the predecoder") > + DebugFlag('Arm') > + DebugFlag('TLBVerbose') > + DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") > + DebugFlag('Predecoder', "Instructions returned by the predecoder") > if env['FULL_SYSTEM']: > Source('interrupts.cc') > Source('stacktrace.cc') > diff -r 483e936f44f0 -r 9228e00459d4 src/arch/mips/SConscript > --- a/src/arch/mips/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/arch/mips/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -41,7 +41,7 @@ > Source('dsp.cc') > > SimObject('MipsTLB.py') > - TraceFlag('MipsPRA') > + DebugFlag('MipsPRA') > > if env['FULL_SYSTEM']: > SimObject('MipsSystem.py') > diff -r 483e936f44f0 -r 9228e00459d4 src/arch/power/SConscript > --- a/src/arch/power/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/arch/power/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -45,7 +45,7 @@ > Source('utility.cc') > > SimObject('PowerTLB.py') > - TraceFlag('Power') > + DebugFlag('Power') > > if not env['FULL_SYSTEM']: > Source('process.cc') > diff -r 483e936f44f0 -r 9228e00459d4 src/arch/sparc/SConscript > --- a/src/arch/sparc/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/arch/sparc/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -44,8 +44,8 @@ > SimObject('SparcNativeTrace.py') > > SimObject('SparcTLB.py') > - TraceFlag('Sparc', "Generic SPARC ISA stuff") > - TraceFlag('RegisterWindows', "Register window manipulation") > + DebugFlag('Sparc', "Generic SPARC ISA stuff") > + DebugFlag('RegisterWindows', "Register window manipulation") > > if env['FULL_SYSTEM']: > SimObject('SparcSystem.py') > diff -r 483e936f44f0 -r 9228e00459d4 src/arch/x86/SConscript > --- a/src/arch/x86/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/arch/x86/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -66,14 +66,14 @@ > SimObject('X86NativeTrace.py') > > SimObject('X86TLB.py') > - TraceFlag('Predecoder', "Predecoder debug output") > - TraceFlag('X86', "Generic X86 ISA debugging") > + DebugFlag('Predecoder', "Predecoder debug output") > + DebugFlag('X86', "Generic X86 ISA debugging") > > if env['FULL_SYSTEM']: > - TraceFlag('LocalApic', "Local APIC debugging") > - TraceFlag('PageTableWalker', \ > + DebugFlag('LocalApic', "Local APIC debugging") > + DebugFlag('PageTableWalker', \ > "Page table walker state machine debugging") > - TraceFlag('Faults', "Trace all faults/exceptions/traps") > + DebugFlag('Faults', "Trace all faults/exceptions/traps") > > SimObject('X86LocalApic.py') > SimObject('X86System.py') > diff -r 483e936f44f0 -r 9228e00459d4 src/base/SConscript > --- a/src/base/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/base/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -73,18 +73,18 @@ > > Source('stats/text.cc') > > -TraceFlag('Annotate', "State machine annotation debugging") > -TraceFlag('AnnotateQ', "State machine annotation queue debugging") > -TraceFlag('AnnotateVerbose', "Dump all state machine annotation details") > -TraceFlag('GDBAcc', "Remote debugger accesses") > -TraceFlag('GDBExtra', "Dump extra information on reads and writes") > -TraceFlag('GDBMisc', "Breakpoints, traps, watchpoints, etc.") > -TraceFlag('GDBRead', "Reads to the remote address space") > -TraceFlag('GDBRecv', "Messages received from the remote application") > -TraceFlag('GDBSend', "Messages sent to the remote application") > -TraceFlag('GDBWrite', "Writes to the remote address space") > -TraceFlag('SQL', "SQL queries sent to the server") > -TraceFlag('StatEvents', "Statistics event tracking") > +DebugFlag('Annotate', "State machine annotation debugging") > +DebugFlag('AnnotateQ', "State machine annotation queue debugging") > +DebugFlag('AnnotateVerbose', "Dump all state machine annotation details") > +DebugFlag('GDBAcc', "Remote debugger accesses") > +DebugFlag('GDBExtra', "Dump extra information on reads and writes") > +DebugFlag('GDBMisc', "Breakpoints, traps, watchpoints, etc.") > +DebugFlag('GDBRead', "Reads to the remote address space") > +DebugFlag('GDBRecv', "Messages received from the remote application") > +DebugFlag('GDBSend', "Messages sent to the remote application") > +DebugFlag('GDBWrite', "Writes to the remote address space") > +DebugFlag('SQL', "SQL queries sent to the server") > +DebugFlag('StatEvents', "Statistics event tracking") > > CompoundFlag('GDBAll', > [ 'GDBMisc', 'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend', 'GDBRecv', > diff -r 483e936f44f0 -r 9228e00459d4 src/base/vnc/SConscript > --- a/src/base/vnc/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/base/vnc/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -42,7 +42,7 @@ > if env['FULL_SYSTEM']: > SimObject('VncServer.py') > Source('vncserver.cc') > - TraceFlag('VNC') > + DebugFlag('VNC') > > Source('convert.cc') > > diff -r 483e936f44f0 -r 9228e00459d4 src/cpu/SConscript > --- a/src/cpu/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/cpu/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -137,7 +137,7 @@ > > if env['USE_CHECKER']: > Source('checker/cpu.cc') > - TraceFlag('Checker') > + DebugFlag('Checker') > checker_supports = False > for i in CheckerSupportedCPUList: > if i in env['CPU_MODELS']: > @@ -149,32 +149,32 @@ > print ", please set USE_CHECKER=False or use one of those CPU models" > Exit(1) > > -TraceFlag('Activity') > -TraceFlag('Commit') > -TraceFlag('Context') > -TraceFlag('Decode') > -TraceFlag('DynInst') > -TraceFlag('ExecEnable') > -TraceFlag('ExecCPSeq') > -TraceFlag('ExecEffAddr') > -TraceFlag('ExecFaulting', 'Trace faulting instructions') > -TraceFlag('ExecFetchSeq') > -TraceFlag('ExecOpClass') > -TraceFlag('ExecRegDelta') > -TraceFlag('ExecResult') > -TraceFlag('ExecSpeculative') > -TraceFlag('ExecSymbol') > -TraceFlag('ExecThread') > -TraceFlag('ExecTicks') > -TraceFlag('ExecMicro') > -TraceFlag('ExecMacro') > -TraceFlag('ExecUser') > -TraceFlag('ExecKernel') > -TraceFlag('ExecAsid') > -TraceFlag('Fetch') > -TraceFlag('IntrControl') > -TraceFlag('PCEvent') > -TraceFlag('Quiesce') > +DebugFlag('Activity') > +DebugFlag('Commit') > +DebugFlag('Context') > +DebugFlag('Decode') > +DebugFlag('DynInst') > +DebugFlag('ExecEnable') > +DebugFlag('ExecCPSeq') > +DebugFlag('ExecEffAddr') > +DebugFlag('ExecFaulting', 'Trace faulting instructions') > +DebugFlag('ExecFetchSeq') > +DebugFlag('ExecOpClass') > +DebugFlag('ExecRegDelta') > +DebugFlag('ExecResult') > +DebugFlag('ExecSpeculative') > +DebugFlag('ExecSymbol') > +DebugFlag('ExecThread') > +DebugFlag('ExecTicks') > +DebugFlag('ExecMicro') > +DebugFlag('ExecMacro') > +DebugFlag('ExecUser') > +DebugFlag('ExecKernel') > +DebugFlag('ExecAsid') > +DebugFlag('Fetch') > +DebugFlag('IntrControl') > +DebugFlag('PCEvent') > +DebugFlag('Quiesce') > > CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr', > 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta', > diff -r 483e936f44f0 -r 9228e00459d4 src/cpu/inorder/SConscript > --- a/src/cpu/inorder/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/cpu/inorder/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -34,28 +34,28 @@ > SimObject('InOrderCPU.py') > SimObject('InOrderTrace.py') > > - TraceFlag('ResReqCount') > - TraceFlag('InOrderStage') > - TraceFlag('InOrderStall') > - TraceFlag('InOrderCPU') > - TraceFlag('RegDepMap') > - TraceFlag('InOrderDynInst') > - TraceFlag('Resource') > - TraceFlag('InOrderAGEN') > - TraceFlag('InOrderFetchSeq') > - TraceFlag('InOrderTLB') > - TraceFlag('InOrderCachePort') > - TraceFlag('InOrderBPred') > - TraceFlag('InOrderDecode') > - TraceFlag('InOrderExecute') > - TraceFlag('InOrderInstBuffer') > - TraceFlag('InOrderUseDef') > - TraceFlag('InOrderMDU') > - TraceFlag('InOrderGraduation') > - TraceFlag('ThreadModel') > - TraceFlag('RefCount') > - TraceFlag('AddrDep') > - TraceFlag('SkedCache') > + DebugFlag('ResReqCount') > + DebugFlag('InOrderStage') > + DebugFlag('InOrderStall') > + DebugFlag('InOrderCPU') > + DebugFlag('RegDepMap') > + DebugFlag('InOrderDynInst') > + DebugFlag('Resource') > + DebugFlag('InOrderAGEN') > + DebugFlag('InOrderFetchSeq') > + DebugFlag('InOrderTLB') > + DebugFlag('InOrderCachePort') > + DebugFlag('InOrderBPred') > + DebugFlag('InOrderDecode') > + DebugFlag('InOrderExecute') > + DebugFlag('InOrderInstBuffer') > + DebugFlag('InOrderUseDef') > + DebugFlag('InOrderMDU') > + DebugFlag('InOrderGraduation') > + DebugFlag('ThreadModel') > + DebugFlag('RefCount') > + DebugFlag('AddrDep') > + DebugFlag('SkedCache') > > CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', > 'InOrderCPU', > 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', > 'InOrderBPred', > diff -r 483e936f44f0 -r 9228e00459d4 src/cpu/o3/SConscript > --- a/src/cpu/o3/SConscript Thu Jun 02 17:36:18 2011 -0700 > +++ b/src/cpu/o3/SConscript Thu Jun 02 17:36:21 2011 -0700 > @@ -33,9 +33,9 @@ > Import('*') > > if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: > - TraceFlag('CommitRate') > - TraceFlag('IEW') > - TraceFlag('IQ') > + DebugFlag('CommitRate') > + DebugFlag('IEW') > + DebugFlag('IQ') > > if 'O3CPU' in env['CPU_MODELS']: > SimObject('FUPool.py') > @@ -64,15 +64,15 @@ > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
