> On 2011-06-08 17:11:26, Brad Beckmann wrote: > > This looks fine to me. I assume that if a controller doesn't include a > > setPermission or getPermission function, the compiler error message is the > > same as when a controller doesn't specify a getState function. Correct?
Currently SLICC does not output any error if set/getState() or set/getAccessPermission() are missing. But I have patch in the queue which enables catching these errors in SLICC. For now GCC outputs that a particular function has not been implemented. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/684/#review1301 ----------------------------------------------------------- On 2011-06-06 14:45:22, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/684/ > ----------------------------------------------------------- > > (Updated 2011-06-06 14:45:22) > > > Review request for Default. > > > Summary > ------- > > Ruby: Correctly set access permissions for directory entries > The access permissions for the directory entries are not being set correctly. > This is because pointers are not used for handling directory entries. > function. get and set functions for access permissions have been added to the > Controller state machine. The changePermission() function provided by the > AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC > code once again. The set_permission() functionality has been removed. > > NOTE: Each protocol will have to define these get and set functions in order > to compile successfully. > > > Diffs > ----- > > src/mem/protocol/MESI_CMP_directory-L1cache.sm b9ba22cb23f2 > src/mem/protocol/MESI_CMP_directory-L2cache.sm b9ba22cb23f2 > src/mem/protocol/MESI_CMP_directory-dir.sm b9ba22cb23f2 > src/mem/protocol/MESI_CMP_directory-dma.sm b9ba22cb23f2 > src/mem/protocol/MI_example-cache.sm b9ba22cb23f2 > src/mem/protocol/MI_example-dir.sm b9ba22cb23f2 > src/mem/protocol/MI_example-dma.sm b9ba22cb23f2 > src/mem/protocol/MOESI_CMP_directory-L1cache.sm b9ba22cb23f2 > src/mem/protocol/MOESI_CMP_directory-L2cache.sm b9ba22cb23f2 > src/mem/protocol/MOESI_CMP_directory-dir.sm b9ba22cb23f2 > src/mem/protocol/MOESI_CMP_directory-dma.sm b9ba22cb23f2 > src/mem/protocol/MOESI_CMP_token-L1cache.sm b9ba22cb23f2 > src/mem/protocol/MOESI_CMP_token-L2cache.sm b9ba22cb23f2 > src/mem/protocol/MOESI_CMP_token-dir.sm b9ba22cb23f2 > src/mem/protocol/MOESI_CMP_token-dma.sm b9ba22cb23f2 > src/mem/protocol/MOESI_hammer-cache.sm b9ba22cb23f2 > src/mem/protocol/MOESI_hammer-dir.sm b9ba22cb23f2 > src/mem/protocol/MOESI_hammer-dma.sm b9ba22cb23f2 > src/mem/protocol/Network_test-cache.sm b9ba22cb23f2 > src/mem/protocol/Network_test-dir.sm b9ba22cb23f2 > src/mem/protocol/RubySlicc_Types.sm b9ba22cb23f2 > src/mem/ruby/slicc_interface/AbstractController.hh b9ba22cb23f2 > src/mem/slicc/ast/MethodCallExprAST.py b9ba22cb23f2 > src/mem/slicc/symbols/StateMachine.py b9ba22cb23f2 > > Diff: http://reviews.m5sim.org/r/684/diff > > > Testing > ------- > > Passes regression tests and 10000 loads with ruby random tester. > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
