In almost all cases the bits that control thing like enabling/disabling caches/prefechers/branch predictors/etc are ignored by gem5. The presence of these types of structures is dependent on the gem5 configuration and not the architecture control registers. By default there is no prefetcher enabled in SPARC.
Ali On Jul 9, 2011, at 12:06 AM, Hamid Reza Khaleghzadeh wrote: > > Hi all, > > I want to disable hardware prefetcher of simulated machine. In Linux, this is > done via MSR register. Could you tell me how I can disable hardware > prefetcher in SPARC and Solaris? > > Thanks > > > > -- > Hamid Reza Khaleghzadeh > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
