A better question might be where are you looking for those files? The gem5 memory system has the cache information auto-generated by the SLICC. You'll need to go to gem5.org and read the docs to figure out the internals of that, but also you'll need to go to src/mem/<your_protocol>/ and look in the *.sm files to find the L2CacheController specification and figure out what latencies you have to toggle to get the desired behavior.
On Tue, Aug 2, 2011 at 1:54 AM, Hamid Reza Khaleghzadeh < [email protected]> wrote: > Hi > > Thanks for your fast reply but I cannot find any fields about miss/hit > latency for L2 cache. > > > On Tue, Aug 2, 2011 at 10:23 AM, Hamid Reza Khaleghzadeh < > [email protected]> wrote: > >> Hi >> >> I want to change L2 miss and hit latency in Gem5. Could you tell me how I >> can do this? by the way, Used coherency protocol is MOESI-CMP-directory. >> >> Thanks >> >> >> >> -- >> Hamid Reza Khaleghzadeh >> > > > > -- > Hamid Reza Khaleghzadeh > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- - Korey
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