I don't think it is. When an instruction executes, it puts together a
memory request and hands that to the CPU. The CPU uses the TLB defined
by the ISA to translate the request which is where a decision is made
about whether the access is allowed. If the TLB didn't decide there
needs to be a fault, the CPU takes the request and uses it to generate
one or more packets which it sends into the memory system to access
the data. The packet itself is more or less just a transaction on the
memory system and doesn't have to involve a processor at all. A
request has more information like that, but it still doesn't have any
information about the mode of the CPU. The TLB makes decisions about
the request potentially using the mode, but that's about as close as
it gets.
Gabe
Quoting Carole-Jean Wu <[email protected]>:
Hi Nilay,
Thanks for your response. Do you know where the processor info is used to
create a packet specifically?
Thanks,
Carole
On Sun, Aug 7, 2011 at 11:56 AM, Nilay Vaish <[email protected]> wrote:
On Sat, 6 Aug 2011, Carole-Jean Wu wrote:
Hi,
I am studying the interaction between user-mode and system-mode memory
reference using gem5. I am finding that all references are passed in as
supervisor mode references in system/RubyPort.cc recv_timing.
As a result, the information of RubyAccessMode is loss after the request
leaves processor issue engine.
Does anyone know how to appropriate set the RubyAccessMode in RubyPort.cc
to
make this field hold valid information?
RubyRequest is created using a packet, so the packet should have the
information on the mode of the processor. I do not know if it has the info,
but if this info exists with the processor that generated the packet, then
it is easy to pass it in the packet.
--
Nilay
______________________________**_________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
