On Tue, Jun 14, 2011 at 4:18 PM, Dawei Wang <david.albert.w...@gmail.com> wrote: > Hello, everyone > Now I am using M5 to simulate 4-core CPU. When I saw the stats.txt reports, > here are some questions showing below. > 1. For some L2 statistic parameters, there are 5 or 6 different values, for > example > system.l2.occ_blocks::0 4296.306219 # Average occupied blocks per context > system.l2.occ_blocks::1 4219.322094 # Average occupied blocks per context > system.l2.occ_blocks::2 4222.702362 # Average occupied blocks per context > system.l2.occ_blocks::3 4224.841879 # Average occupied blocks per context > system.l2.occ_blocks::4 7387.035504 # Average occupied blocks per context > system.l2.occ_percent::0 0.131113 # Average percentage of cache occupancy > system.l2.occ_percent::1 0.128763 # Average percentage of cache occupancy > system.l2.occ_percent::2 0.128867 # Average percentage of cache occupancy > system.l2.occ_percent::3 0.128932 # Average percentage of cache occupancy > system.l2.occ_percent::4 0.225434 # Average percentage of cache occupancy > Usually, the fifth value is the summary of the first four. However for the > "occ_blocks", and "occ_persent", it is not the summary. Does anybody know > what the fifth value means?
The +1 is all the other cache requests other than CPUs, it's confusing I have to admit. :-( > 2. For 6 different values case, for example > system.l2.overall_hits::0 32916188 # number of overall hits > system.l2.overall_hits::1 32991021 # number of overall hits > system.l2.overall_hits::2 30251740 # number of overall hits > system.l2.overall_hits::3 32917713 # number of overall hits > system.l2.overall_hits::4 0 # number of overall hits > system.l2.overall_hits::total 129076662 # number of overall hits > Where is "system.l2.overall_hits::4" coming from? The last one is always the +1 from devices other than CPUs cache requests, it can be zero. > 3. I have read all stats.txt, and I didn't find any main memory access > statistic. So can I deduce the memory read and write from L2 statistics? For > example, > # main memory read requests == l2.replacement > # main memory write requests == l2.writeback > is that correct? The L2 is a non-blocking cache. For write, look at write buffer write backs, and for read, look at MSHR, also if hardware prefetcher is enabled in L2, that generates read requests too. > > Many thanks in advance. > Bests > Dawei > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
