Hi,
I added a debug message in Cache<TagStore>::getTimingPacket()
pkt = getBusPacket(tgt_pkt, blk, mshr->needsExclusive());
if ( pkt ) {
DPRINTF(Cache, "getting bus pkt=%s \n", pkt);
}
mshr->isForward = (pkt == NULL);
Then in the verbose messages I see:
1254053000: system.cpu.dcache-pf: Requesting a hw_pf to issue
1254053000: system.cpu.dcache-pf: returning 0xbc000
1254053000: system.switch_cpus.iew.lsq-dport: received pkt for
addr:0xbc000 HardPFReq
1254053000: system.cpu.dcache: getting bus pkt=0x2a31410
1254053000: system.toL2bus: recvTiming: src 2 dst -1 ReadReq 0xbc000
1254053000: system.switch_cpus.fetch-iport: Received timing to Icache in fetch
1254053000: system.l2: ReadReq bc000
1254053000: system.toL2bus: The bus is now occupied from tick
1254053000 to 1254054000
Later I see:
1254062000: system.switch_cpus: Scheduling next tick!
1254063000: system.l2: getting bus pkt=0x2a31aa0
1254063000: system.membus: recvTiming: src 1 dst -1 ReadReq 0xbc000
1254063000: system.membus: The bus is now occupied from tick
1254063000 to 1254064000
As you can see for one ReadReq 0xbc000, there are two packets: 1) for
dcache and 2) for l2.
What I can not figure out is how packets are sent from dcache to l2.
Which function do the job?
Thanks for any hint.
--
// Naderan *Mahmood;
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