Hi It seems that when the simulator switches to O3CPU, the cache blocks that were inserted to cache from AtomicSimpleCPU, they still remain in cache. In another word, I noticed that after switching to O3CPU, some first accesses hit in cache.
On the other hand, the statistics are reset to zero after swtiching from Simple to O3. I think that make the simulation inaccurate. For the above example, normally we expect that some first accesses are missed in cache. However with current implementation, they hit in cache and we increment the hit counter. Is there any way to purge the cache, registers and other queues after switching? Thanks and regards, -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
