Hi, I want to model deeper pipeline in X86 simulation, around 20-31 stages. The ISCA tutorial slide mentioned that this could be achieved by adding varying amounts of delay in between the existing 7 stages in O3CPU.py. However, when I add some delays, the simulation aborts due to assert failure. Has anyone tried to do this ? Or anyone has any ideas on how this could be done ?
Thanks a lot for your help ! -- Regards, Ankita Graduate Student Department of Computer Science University of Texas at Austin
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