Good practice is probably to wait at least 24-48 hours to re-ask the same question on the mailing list.
As gem5 is an open source community of researchers, students and industry workers, it's unreasonable to expect someone to always be available to immediately answer your questions. With respect to your question, the gem5 CPU models aren't specific to any ISA. There isnt a "x86" or "mips" model. The ISA is a separate entity that can be plugged into a CPU. Please read the tutorial slides for information on that (gem5.org). Now, The O3 CPU model uses a merged physical register file (unified) as far as I can recall. But again, this is generic CPU model that is not specific to any particular ISA. On Fri, May 11, 2012 at 5:31 AM, Aziz <[email protected]> wrote: > Doesn't anybody knows about register file in x86 model? Is it unified or > split, or configurable? > > > On Thu, May 10, 2012 at 1:02 AM, Aziz Eker > <[email protected]>wrote: > >> Hi, >> >> I found that gem5 x86 model is "similar to AMD's version of the >> architecture than Intel's but not strictly like either". My question >> is, does it support unified register file (as in pentium 4) or split >> register file (as in P6 architecture)? >> >> Thanks in advance, >> Aziz >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- - Korey
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